Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-7  
9.6.1.1 SROM_BW 
 Base Address: 0x1225_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0009 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0=
ByteEnable3=[15]=RW=
nW BE/nBE (for UB/LB) control for Memory Bank3=
0 = Not using UB/LB (XsramBEn[1:0] is dedicated 
nW BE[1:0])=
1 = Using UB/LB (XsramBEn[1:0]=is dedicated=
nBE[1:0])=
0=
WaitEnable3=[14]=RW=
Wait enable control for Memory Bank3==
0 = Disables WAIT=
1...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-8  
Name Bit Type Description Reset Value 
1 = Using UB/LB (XsramBEn[1:0] is dedicated 
nBE[1:0]) 
WaitEnable1 [6] RW 
Wait enable control for Memory Bank1 
0 = Disables WAIT 
1 = Enables W AIT 
0 
AddrMode1 [5] RW 
Select SROM ADDR Base for Memory Bank1 
0 = SROM_ADDR is Half-word base address.  
(SROM_ADDR[15:0]  HADDR[16:1]) 
1 = SROM_ADDR is byte base address 
(SROM_ADDR[15:0]  HADDR[15:0]) 
NOTE: When DataW idth1 is 0, SROM_ADDR is 
byte...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-9  
9.6.1.2 SROM_BCn (n = 0 to 3) 
 Base Address: 0x1225_0000 
 Address = Base Address + 0x0004, 0x0008, 0x000C, 0x0010, Reset Value = 0x000F_0000 
Name Bit Type Description Reset Value 
Tacs [31:28] RW 
Address set-up before nGCS 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
………….=
1100 ==12 Clocks=
1101== 13 Clocks=
1110 = 14 Clocks=
1111 = 15 Clocks=
NOTE: More 1=–=2 cycles according to bus i/f status=
0000=...

Samsung Confidential  
Exynos 5250_UM 9 SROM Controller 
 9-10  
Name Bit Type Description Reset Value 
Tcah [11:8] RW 
Address holding time after nGCSn 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
…………. 
1100 = 12 Clocks 
1101 = 13 Clocks 
1110 = 14 Clocks 
1111 = 15 Clocks 
NOTE: More 1 – 2 cycles according to bus I/F status 
0000 
Tacp [7:4] RW 
Page mode access cycle @ Page mode 
0000 = 0 Clock 
0001 = 1 Clocks 
0010 = 2 Clocks 
0011 = 3 Clocks 
…………. 
1100 = 12 Clocks 
1101 =...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-1  
10 Pulse Width Modulation Timer 
10.1 Overview 
The Exynos 5250 has five 32-bit Pulse Width Modulation (PWM) timers. These Timers generate internal interrupts 
for the ARM subsystem. Additionally, Timers 0, 1, 2 and 3 include a PWM function that drives an external I/O 
signal. The PWM in Timer 0 has an optional dead-zone generator capability to support a large current device. 
Timer 4 is internal timer without output pins....

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-2  
Figure 10-1 illustrates an example of a PW M cycle: 
 
    Figure 10-1   PWM Cycle 
Steps in PWM Cycle: 
 Initialize the TCNTBn register with 159 (50 + 109) and TCMPBn with 109.  
 Start Timer: Sets the start bit and manually updates this bit to OFF. 
The TCNTBn value of 159 is loaded into the down-counter. Then, the output TOUTn is set to low. 
 When down-counter counts down the value from TCNTBn to value in the TCMPBn...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-3  
Figure 10-2 illustrates the clock generation scheme for individual PWM Channels: 
 
    Figure 10-2   PWM TIMER Clock Tree Diagram 
The Figure 10-2 shows the clock generation scheme for individual PWM Channels. 
Each Timer can generate level interrupts. 
 6:1MUXControlLogic 0
ControlLogic 4
ControlLogic 3
ControlLogic 2
ControlLogic 1
8BITPRESCALER0
DeadZoneGenerator
TCNTB0TCMPB0
TCNTB1TCMPB1
TCNTB2TCMPB2
TCNTB3TCMPB3
TCNTB4...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-4  
10.2 Features 
PW M supports these features: 
 Five 32-bit Timers 
 Two 8-bit Clock Prescalers that provide first level of division for the PCLK, and five Clock Dividers and 
Multiplexers that provide second level of division for the Prescaler clock 
 Programmable Clock Select Logic for individual PWM Channels 
 Four Independent PW M Channels with Programmable Duty Control and Polarity 
 Static Configuration: PWM is...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-5  
10.3 PWM Operation 
10.3.1 Prescaler and Divider 
An 8-bit prescaler and 3-bit divider generates these output frequencies. Table 10-1 lists the minimum and 
maximum resolution based on Prescaler and Clock Divider values: 
Table 10-1   Minimum and Maximum Resolution based on Prescaler and Clock Divider Values 
4-bit Divider Settings Minimum Resolution 
(Prescaler Value = 1) 
Maximum Resolution 
(Prescaler Value = 255) 
Maximum...

Samsung Confidential  
Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-6  
To generate interrupt at intervals three-cycle of XpwmTOUTn, set TCNTBn, TCMPBn and TCON.    
Steps to generate interrupt:  
1. Set TCNTBn = 3 and TCMPBn = 1. 
2. Set auto-reload = 1 and manual update = 1.  
 When manual update bit is 1, the TCNTBn and TCMPBn values are loaded to TCNTn and TCMPn. 
3. Set TCNTBn = 2 and TCMPBn = 0 for the next operation.  
4. Set auto-reload = 1 and manual update = 0.  
 If you set manual...