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Samsung Exynos 5 User Manual

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Page 581

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-3  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG4 
MCUIOP [7] MCUIOP_CTIIRQ MCUIOP [6] MCUIOP_PMUIRQ 
MCUISP [5] MCUISP_CTIIRQ MCUISP [4] MCUISP_PMUIRQ 
SYSMMU[19:16] 
[3] SYSMMU_JPEGX[1] 
System MMU [2] SYSMMU_JPEGX[0] 
[1] SYSMMU_ROTATOR[1] 
[0] SYSMMU_ROTATOR[0] 
INTG5 SYSMMU[27:20] 
[7] SYSMMU_3DNR[1] 
System MMU 
[6] SYSMMU_3DNR[0] 
[5] SYSMMU_MCUISP[1] 
[4] SYSMMU_MCUISP[0] 
[3]...

Page 582

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-4  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
[3] Reserved 
[2] Reserved 
[1] Reserved 
[0] Reserved 
INTG9 
RSVD [7] Reserved – [6] Reserved 
SYSMMU[47:46] [5] SYSMMU_DIS1[1] System MMU [4] SYSMMU_DIS1[0] 
RSVD 
[3] Reserved 
– [2] Reserved 
[1] Reserved 
[0] Reserved 
INTG10 
SYSMMU[49:48] 
[7] SYSMMU_ISP[1] 
System MMU [6] SYSMMU_ISP[0] 
[5] SYSMMU_DIS0[1] 
[4] SYSMMU_DIS0[0] 
DP1 [3] DP1 DP1...

Page 583

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-5  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
INTG16 PEREV 
[7] Reserved 
CDREX block 
[6] Reserved 
[5] Reserved 
[4] Reserved 
[3] PEREV_M1_CDREX 
[2] PEREV_M0_CDREX 
[1] PEREV_A1_CDREX 
[0] PEREV_A0_CDREX 
INTG17 
RSVD [7:4] Reserved – 
C2C 
[3] SSCM_PULSE_IRQ_C2CIF[1] 
CDREX block [2] SSCM_PULSE_IRQ_C2CIF[0] 
[1] SSCM_IRQ_C2CIF[1] 
[0] SSCM_IRQ_C2CIF[0] 
INTG18 
DISP1 
[7] DISP1[3] 
DISP1 [6]...

Page 584

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-6  
Combiner 
Group ID 
Combined Interrupt 
Source Name Bit Interrupt Source Source Block 
[2] CPU_PARITYFAILSCU[1] 
[1] CPU_nCNTHPIRQ[1] 
[0] PARITYFAIL[1] 
INTG23 
RSVD 
[7] Reserved 
– [6] Reserved 
[5] Reserved 
MCT_G[1:0] [4] MCT_G1 MCT [3] MCT_G0 
RSVD [2] Reserved – [1] Reserved 
EINT[0] [0] EINT[0] External interrupt 
INTG24 
SYSMMU[57:56] [6] SYSMMU_G2D[1] System MMU [5] SYSMMU_G2D[0] 
RSVD [4:3] Reserved – 
SYSMMU[55:54] [2]...

Page 585

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-7  
7.4 Functional Description 
An interrupt enable bit controls an interrupt source in an interrupt group. IESRn registers and IECRn registers 
control the interrupt enable bits. IESRn register can toggle an interrupt bit to 1. If you write 1 to a bit position on 
IESRn, the corresponding bit on the interrupt enable bits are set to 1. Alternatively, IECRn register can toggle an 
interrupt enable bit to 0. If you write 1 to a bit position on...

Page 586

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-8  
7.5 Register Description 
7.5.1 Register Map Summary 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
Register Offset Description Reset Value 
IESR0 0x0000 Interrupt enable set register for group 0 to 3 0x00000000 
IECR0 0x0004 Interrupt enable clear register for group 0 to 3 0x00000000 
ISTR0 0x0008 Interrupt status register for group 0 to 3 Undefined 
IMSR0 0x000C Interrupt masked status register for group 0 to 3...

Page 587

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-9  
7.5.1.1 IESR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting  
1 = Sets the interrupt enable bit to 1. 
Read 
The...

Page 588

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-10  
7.5.1.2 IECR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] RW Clears the corresponding interrupt enable bit to 
0.  
If the interrupt enable bit is cleared, the interrupt 
is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0 
Read 
The current...

Page 589

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-11  
Name Bit Type Description Reset Value 
1 = Enables 
  

Page 590

Samsung Confidential  
Exynos 5250_UM 7 Interrupt Combiner 
 7-12  
7.5.1.3 ISTR0 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0008, Reset Value = Undefined 
Name Bit Type Description Reset Value 
SYSMMU_SCALERPISP[1] [31] R 
Interrupt pending status  
The corresponding interrupt enable bit does not 
affect this pending status. 
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
SYSMMU_SCALEoPISP[0]=[30]=o=–=...
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