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Samsung Exynos 5 User Manual

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    Page 541

    Page 541 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-175 5.9.1.165 CLK_GATE_BLOCK  Base Address: 0x1002_0000  Address = Base Address + 0x0980, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:8] –=Reserved=0xFF_FFFF= CLK_ACm=x7]=RW= Gating all=Clocks for=ACP_BLK (ACPG2D)= 0 ==Masks= 1 = Passes= 0x1= RSVD=x6]=–=Reserved=0x1= CLK_DISP1=[5]=RW= Gating all=Clocks for=DISP1_BLK (FIMD1, MIE1, DSIM1)= 0 = Masks= 1 = Passes= 0x1= RSVD=x4]=–=Reserved=0x1= CLK_GSCL=[3]=RW=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-175  
5.9.1.165 CLK_GATE_BLOCK 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0980, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0xFF_FFFF=
CLK_ACm=x7]=RW=
Gating all=Clocks for=ACP_BLK (ACPG2D)=
0 ==Masks=
1 = Passes=
0x1=
RSVD=x6]=–=Reserved=0x1=
CLK_DISP1=[5]=RW=
Gating all=Clocks for=DISP1_BLK (FIMD1, MIE1, 
DSIM1)=
0 = Masks=
1 = Passes=
0x1=
RSVD=x4]=–=Reserved=0x1=
CLK_GSCL=[3]=RW=...

    Page 542

    Page 542 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-176 5.9.1.167 CLKOUT_CMU_TOP  Base Address: 0x1002_0000  Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables= 0x1= RSVD=x15:14]=–=Reserved=0x0= DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0= RSVD=[7:5]=–=Reserved=0x0= MUX_SEi=[4:0]=RW= 00000 = EPLL_FOUT= 00001 = VPLL_FOUT= 00010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-176  
5.9.1.167 CLKOUT_CMU_TOP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = EPLL_FOUT=
00001 = VPLL_FOUT=
00010 =...

    Page 543

    Page 543 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-177 5.9.1.168 CLKOUT_CMU_TOP_DIV_STAT  Base Address: 0x1002_0000  Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] –=Reserved=0x0= DIV_STAT=[0]=o= DIV_CLKOUT Status= 0 = Stable= 1 = Divider is changing= 0x0= = 5.9.1.169 CLK_SRC_LEX  Base Address: 0x1002_0000  Address = Base Address + 0x4200, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1]... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-177  
5.9.1.168 CLKOUT_CMU_TOP_DIV_STAT 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.169 CLK_SRC_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1]...

    Page 544

    Page 544 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-178 5.9.1.171 CLK_DIV_LEX  Base Address: 0x1002_0000  Address = Base Address + 0x4500, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:11] –=Reserved=0x0= ATCLK_LEu= _RATIO=[10:8]=RW= ATCLK_LEX clock divider oatio= ATCLK_LEu= = MOUT_ATCLK_LEX/(ATCLK_LEX_RATIO + 1)= 0x0= RSVD=[7]=–=Reserved=0x0= PCLK_LEX= _RATIO=[6:4]=RW= PCLK_LEX clock divider=oatio= PCLK_LEX= = ACLK_266 /(PCLK_LEX_RATIO + 1)= 0x0=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-178  
5.9.1.171 CLK_DIV_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:11] –=Reserved=0x0=
ATCLK_LEu=
_RATIO=[10:8]=RW=
ATCLK_LEX clock divider oatio=
ATCLK_LEu=
= MOUT_ATCLK_LEX/(ATCLK_LEX_RATIO + 1)=
0x0=
RSVD=[7]=–=Reserved=0x0=
PCLK_LEX=
_RATIO=[6:4]=RW=
PCLK_LEX clock divider=oatio=
PCLK_LEX=
= ACLK_266 /(PCLK_LEX_RATIO + 1)=
0x0=...

    Page 545

    Page 545 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-179 5.9.1.173 CLK_GATE_IP_LEX  Base Address: 0x1002_0000  Address = Base Address + 0x4800, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:0] –=Reserved=0xFFFF_FFFc= = 5.9.1.174 CLKOUT_CMU_LEX  Base Address: 0x1002_0000  Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-179  
5.9.1.173 CLK_GATE_IP_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:0] –=Reserved=0xFFFF_FFFc=
=
5.9.1.174 CLKOUT_CMU_LEX 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x4A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=...

    Page 546

    Page 546 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-180 5.9.1.176 CLK_DIV_R0X  Base Address: 0x1002_0000  Address = Base Address + 0x8500, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:23] –=Reserved=0x0= PCLK_R0X_RATIO=[6:4]=RW= DIs_PR0u=Clock divider Ratio= PCLK_R0u= = ACLK_26S/(PCLK_R0X_RATIO + 1)= 0x0= RSVD=[3:0]=–=Reserved=0x0= = 5.9.1.177 CLK_DIV_STAT_R0X  Base Address: 0x1002_0000  Address = Base Address + 0x8600, Reset Value = 0x0000_0000 Name Bit... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-180  
5.9.1.176 CLK_DIV_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
PCLK_R0X_RATIO=[6:4]=RW=
DIs_PR0u=Clock divider Ratio=
PCLK_R0u=
= ACLK_26S/(PCLK_R0X_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.177 CLK_DIV_STAT_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8600, Reset Value = 0x0000_0000 
Name Bit...

    Page 547

    Page 547 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-181 5.9.1.179 CLKOUT_CMU_R0X  Base Address: 0x1002_0000  Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables= 0x1= RSVD=x15:14]=–=Reserved=0x0= DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0= RSVD=[7:5]=–=Reserved=0x0= MUX_SEi=[4:0]=RW= 00000 = ACLK_266= 00001 = APLL_DR0X= 00010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-181  
5.9.1.179 CLKOUT_CMU_R0X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x8A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266=
00001 = APLL_DR0X=
00010 =...

    Page 548

    Page 548 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-182 5.9.1.181 CLK_DIV_R1X  Base Address: 0x1002_0000  Address = Base Address + 0xC500, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:23] –=Reserved=0x0= PCLK_R1X_RATIO=[6:4]=RW= DIs_PR1u=clock divider Ratio= PCLK_R1u= = ACLK_26S/(PCLK_R1X_RATIO + 1)= 0x0= RSVD=[3:0]=–=Reserved=0x0= = 5.9.1.182 CLK_DIV_STAT_R1X  Base Address: 0x1002_0000  Address = Base Address + 0xC600, Reset Value = 0x0000_0000 Name Bit... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-182  
5.9.1.181 CLK_DIV_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xC500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
PCLK_R1X_RATIO=[6:4]=RW=
DIs_PR1u=clock divider Ratio=
PCLK_R1u=
= ACLK_26S/(PCLK_R1X_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.182 CLK_DIV_STAT_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xC600, Reset Value = 0x0000_0000 
Name Bit...

    Page 549

    Page 549 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-183 5.9.1.184 CLKOUT_CMU_R1X  Base Address: 0x1002_0000  Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables= 0x1= RSVD=x15:14]=–=Reserved=0x0= DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0= RSVD=[7:5]=–=Reserved=0x0= MUX_SEi=[4:0]=RW= 00000 = ACLK_266= 00001 = APLL_DR1X= 00010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-183  
5.9.1.184 CLKOUT_CMU_R1X 
 Base Address: 0x1002_0000 
 Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266=
00001 = APLL_DR1X=
00010 =...

    Page 550

    Page 550 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-184 5.9.1.187 BPLL_CON0  Base Address: 0x1003_0000  Address = Base Address + 0x0110, Reset Value = 0x00C8_0601 Name Bit Type Description Reset Value ENABLE [31] RW PLL Enable control 0 = Disables 1 = Enables 0x0 RSVD [30] –=Reserved=0x0= LOCKED=[29]=o= PLL Locking indication= 0 = Unlocks= 1 = Locks= 0x0= RSVD=[28:26]=–=Reserved=0x0= MDIV=[25:16]=RW=PLL M Divide Value=0xC8= RSVD=[15:14]=–=Reserved=0x0= PDIV=[13:8]=RW=PLL P Divide... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-184  
5.9.1.187 BPLL_CON0 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0110, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables 
1 = Enables 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks=
1 = Locks=
0x0=
RSVD=[28:26]=–=Reserved=0x0=
MDIV=[25:16]=RW=PLL M Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=PLL P Divide...
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