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Samsung Exynos 5 User Manual

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    Page 491

    Page 491 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-125 5.9.1.103 CLK_SRC_MASK_DISP1_0  Base Address: 0x1002_0000  Address = Base Address + 0x032C, Reset Value = 0x0001_1115 Name Bit Type Description Reset Value RSVD [31:21] –=Reserved=0x0= HDMI_MASh=x20]=RW= Masks output clock of MUX_HDMI= 0 = Masks= 1 = Unmasks= 0x1= RSVD=x19:17]=–=Reserved=0x0= DP1_EXT_MST= _VID_MASh=[1S]=RW= Masks output clock of MUX_DP1_EXT_MST_VIa= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[15:13]=–=Reserved=0x0=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-125  
5.9.1.103 CLK_SRC_MASK_DISP1_0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x032C, Reset Value = 0x0001_1115 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
HDMI_MASh=x20]=RW=
Masks output clock of MUX_HDMI=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x19:17]=–=Reserved=0x0=
DP1_EXT_MST=
_VID_MASh=[1S]=RW=
Masks output clock of MUX_DP1_EXT_MST_VIa=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[15:13]=–=Reserved=0x0=...

    Page 492

    Page 492 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-126 5.9.1.105 CLK_SRC_MASK_FSYS  Base Address: 0x1002_0000  Address = Base Address + 0x0340, Reset Value = 0x1100_1111 Name Bit Type Description Reset Value RSVD [31:29] –=Reserved=0x0= USBDRD30_MASh=[28]=RW= Masks output clock of MUX_USBDRD30= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[31:25]=–=Reserved=0x0= SATA_MASh=[24]=RW= Masks output clock of MUX_SATA= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[23:13]=–=Reserved=0x0= MMC3_MASh=[12]=RW= Masks... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-126  
5.9.1.105 CLK_SRC_MASK_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0340, Reset Value = 0x1100_1111 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
USBDRD30_MASh=[28]=RW=
Masks output clock of MUX_USBDRD30=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[31:25]=–=Reserved=0x0=
SATA_MASh=[24]=RW=
Masks output clock of MUX_SATA=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:13]=–=Reserved=0x0=
MMC3_MASh=[12]=RW=
Masks...

    Page 493

    Page 493 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-127 5.9.1.107 CLK_SRC_MASK_PERIC0  Base Address: 0x1002_0000  Address = Base Address + 0x0350, Reset Value = 0x0100_1111 Name Bit Type Description Reset Value RSVD [31:25] –=Reserved=0x0= PW M_MASh=x24]=RW= Masks output clock of MUX_PWM= 0 = Masks= 1 = Unmasks= 0x1= RSVD=x23:13]=–=Reserved=0x0= UART3_MASK=[12]=RW= Masks output clock of MUX_UART3= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[11:9]=–=Reserved=0x0= UART2_MASK=[8]=RW= Masks output... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-127  
5.9.1.107 CLK_SRC_MASK_PERIC0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0350, Reset Value = 0x0100_1111 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
PW M_MASh=x24]=RW=
Masks output clock of MUX_PWM=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x23:13]=–=Reserved=0x0=
UART3_MASK=[12]=RW=
Masks output clock of MUX_UART3=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART2_MASK=[8]=RW=
Masks output...

    Page 494

    Page 494 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-128 5.9.1.108 CLK_SRC_MASK_PERIC1  Base Address: 0x1002_0000  Address = Base Address + 0x0354, Reset Value = 0x0111_0111 Name Bit Type Description Reset Value RSVD [31:25] –=Reserved=0x0= SPI2_MASh=[24]=RW= Masks output clock of MUX_SPI2= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[23:21]=–=Reserved=0x0= SPI1_MASh=[20]=RW= Masks output clock of MUX_SPI1= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[19:17]=–=Reserved=0x0= SPI0_MASh=[16]=RW= Masks output... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-128  
5.9.1.108 CLK_SRC_MASK_PERIC1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0354, Reset Value = 0x0111_0111 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
SPI2_MASh=[24]=RW=
Masks output clock of MUX_SPI2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:21]=–=Reserved=0x0=
SPI1_MASh=[20]=RW=
Masks output clock of MUX_SPI1=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[19:17]=–=Reserved=0x0=
SPI0_MASh=[16]=RW=
Masks output...

    Page 495

    Page 495 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-129 5.9.1.109 SCLK_SRC_MASK_ISP  Base Address: 0x1002_0000  Address = Base Address + 0x0370, Reset Value = 0x0000_1111 Name Bit Type Description Reset Value RSVD [31:13] –=Reserved=0x0= PW M_ISm_MASh=[12]=RW= Masks output clock of MUX_PWM_ISm= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[11:9]=–=Reserved=0x0= UART_ISP_MASh=[8]=RW= Masks output clock of MUX_UART_ISP= 0 = Masks= 1 = Unmasks= 0x1= RSVD=[7:5]=–=Reserved=0x0= SPI1_ISP_MASh=[4]=RW=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-129  
5.9.1.109 SCLK_SRC_MASK_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0370, Reset Value = 0x0000_1111 
Name Bit Type Description Reset Value 
RSVD [31:13] –=Reserved=0x0=
PW M_ISm_MASh=[12]=RW=
Masks output clock of MUX_PWM_ISm=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART_ISP_MASh=[8]=RW=
Masks output clock of MUX_UART_ISP=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
SPI1_ISP_MASh=[4]=RW=...

    Page 496

    Page 496 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-130 5.9.1.110 CLK_MUX_STAT_TOP0  Base Address: 0x1002_0000  Address = Base Address + 0x0410, Reset Value = 0x1011_1100 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ACLK_300_GSCi= _MID_SEL=[30:28]=o= Selection signal status of=MUX_ACLK_300_GSCL_= MIa= 001 = SCLK_MPLL_USER= 010 = SCLK_BPLL_USER= 1xx = On changing= 0x1= RSVD=[27]=–=Reserved=0x0= ACLK_300_GSCi= _SEL=[26:24]=o= Selection signal status of=MUX_ACLK_300=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-130  
5.9.1.110 CLK_MUX_STAT_TOP0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0410, Reset Value = 0x1011_1100 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_GSCi=
_MID_SEL=[30:28]=o=
Selection signal status of=MUX_ACLK_300_GSCL_=
MIa=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLL_USER=
1xx = On changing=
0x1=
RSVD=[27]=–=Reserved=0x0=
ACLK_300_GSCi=
_SEL=[26:24]=o=
Selection signal status of=MUX_ACLK_300=...

    Page 497

    Page 497 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-131 Name Bit Type Description Reset Value ACLK_300_DISP1 _SEL [2:0] R Selection signal status of MUX_ACLK_300_DISP1 001 = ACLK_300_DISP1_MID 010 = ACLK_300_DISP1_MID1 1xx = On changing 0x1 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-131  
Name Bit Type Description Reset Value 
ACLK_300_DISP1 
_SEL [2:0] R 
Selection signal status of MUX_ACLK_300_DISP1 
001 = ACLK_300_DISP1_MID 
010 = ACLK_300_DISP1_MID1 
1xx = On changing 
0x1

    Page 498

    Page 498 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-132 5.9.1.111 CLK_MUX_STAT_TOP1  Base Address: 0x1002_0000  Address = Base Address + 0x0414, Reset Value = 0x1111_1100 Name Bit Type Description Reset Value RSVD [31:27] –=Reserved=0x0= ACLK_400_G3D_S EL=[30:28]=o= Selection signal status of=MUX_ACLK_400_G3D= 001 = MUX_ACLK_400_G3D_MID= 010 = MUX_ACLK_400_G3D_MID1= 1xx = On changing= 0x1= RSVD=[31:27]=–=Reserved=0x0= ACLK_400_ISP= _SEL=x26:24]=o= Selection signal status... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-132  
5.9.1.111 CLK_MUX_STAT_TOP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0414, Reset Value = 0x1111_1100 
Name Bit Type Description Reset Value 
RSVD [31:27] –=Reserved=0x0=
ACLK_400_G3D_S
EL=[30:28]=o=
Selection signal status of=MUX_ACLK_400_G3D=
001 = MUX_ACLK_400_G3D_MID=
010 = MUX_ACLK_400_G3D_MID1=
1xx = On changing=
0x1=
RSVD=[31:27]=–=Reserved=0x0=
ACLK_400_ISP=
_SEL=x26:24]=o=
Selection signal status...

    Page 499

    Page 499 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-133 5.9.1.112 CLK_MUX_STAT_TOP2  Base Address: 0x1002_0000  Address = Base Address + 0x0418, Reset Value = 0x1111_1100 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= GPLL_SEi=x30:28]=o= Selection signal status of=MUX_GPLL= 001 = XXTI= 010 = FOUT_GPLi= 1xx = On changing= 0x1= RSVD=[31:27]=–=Reserved=0x0= BPLL_USEo_SEL=x26:24]=o= Selection signal status of=MUX_BPLL_USEo= 001 = XXTI= 010 = SCLK_BPLi= 1xx = On changing=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-133  
5.9.1.112 CLK_MUX_STAT_TOP2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0418, Reset Value = 0x1111_1100 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
GPLL_SEi=x30:28]=o=
Selection signal status of=MUX_GPLL=
001 = XXTI=
010 = FOUT_GPLi=
1xx = On changing=
0x1=
RSVD=[31:27]=–=Reserved=0x0=
BPLL_USEo_SEL=x26:24]=o=
Selection signal status of=MUX_BPLL_USEo=
001 = XXTI=
010 = SCLK_BPLi=
1xx = On changing=...

    Page 500

    Page 500 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-134 5.9.1.113 CLK_MUX_STAT_TOP3  Base Address: 0x1002_0000  Address = Base Address + 0x041C, Reset Value = 0x1111_1111 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ACLK_300_GSCi= _SUB_SEL=[30:28]=o= Selection signal status of=MUX_ACLK_300_GSCi= 001== XXTI= 010 = ACLK_300_GSCi= 1xx = On changing= 0x1= RSVD=x27]=–=Reserved=0x0= ACLK_333_SUB= _SEL=x26:24]=o= Selection signal status of=MUX_ACLK_333_SUB= 001 = XXTI= 010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-134  
5.9.1.113 CLK_MUX_STAT_TOP3 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x041C, Reset Value = 0x1111_1111 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_GSCi=
_SUB_SEL=[30:28]=o=
Selection signal status of=MUX_ACLK_300_GSCi=
001== XXTI=
010 = ACLK_300_GSCi=
1xx = On changing=
0x1=
RSVD=x27]=–=Reserved=0x0=
ACLK_333_SUB=
_SEL=x26:24]=o=
Selection signal status of=MUX_ACLK_333_SUB=
001 = XXTI=
010 =...
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