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Samsung Exynos 5 User Manual

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    Page 451

    Page 451 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-85 5.9.1.56 CLK_DIV_SYSLFT  Base Address: 0x1001_0000  Address = Base Address + 0x8900, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:12] –=Reserved=0x0= EFCLK_SYSLFT_R ATIO=x11:8]=RW= SYSLFT EFCLK clock divider ratio,= EFCLK_SYSLFT = SCLK_MPLL/ (EFCLK_SYSLFT_RATIO + 1)= 0x0= RSVD=[7]=–=Reserved=0x0= PCLK_SYSLFT_o ATIO=x6:4]=RW= SYSLFT PCLK clock divider ratio,= PCLK_SYSLFT = ACLK_SYSLFT/= (PCLK_SYSLFT_RATIO... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-85  
5.9.1.56 CLK_DIV_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8900, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:12] –=Reserved=0x0=
EFCLK_SYSLFT_R
ATIO=x11:8]=RW=
SYSLFT EFCLK clock divider ratio,=
EFCLK_SYSLFT = SCLK_MPLL/ 
(EFCLK_SYSLFT_RATIO + 1)=
0x0=
RSVD=[7]=–=Reserved=0x0=
PCLK_SYSLFT_o
ATIO=x6:4]=RW=
SYSLFT PCLK clock divider ratio,=
PCLK_SYSLFT = ACLK_SYSLFT/=
(PCLK_SYSLFT_RATIO...

    Page 452

    Page 452 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-86 5.9.1.58 CLK_GATE_BUS_SYSLFT  Base Address: 0x1001_0000  Address = Base Address + 0x8920, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x7FFF= EFCLh=x16]=ot= Gating EFCLK clock for UFMC= 0 = Masks= 1 = Passes= 0x1= RSVD=x15:0]=–=Reserved=0xFFFF= = 5.9.1.59 CLK_GATE_IP_SYSLFT  Base Address: 0x1001_0000  Address = Base Address + 0x8930, Reset Value = 0xFFFF_FFFF Name Bit Type Description... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-86  
5.9.1.58 CLK_GATE_BUS_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8920, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x7FFF=
EFCLh=x16]=ot=
Gating EFCLK clock for UFMC=
0 = Masks=
1 = Passes=
0x1=
RSVD=x15:0]=–=Reserved=0xFFFF=
=
5.9.1.59 CLK_GATE_IP_SYSLFT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8930, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description...

    Page 453

    Page 453 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-87 5.9.1.61 CLKOUT_CMU_ACP_DIV_STAT  Base Address: 0x1001_0000  Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] –=Reserved=0x0= DIV_STAT=[0]=o= DIV_CLKOUT Status= 0 = Stable= 1 = Divider is changing= 0x0= = 5.9.1.62 UFMC_CONFIG  Base Address: 0x1001_0000  Address = Base Address + 0x8A10, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1]... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-87  
5.9.1.61 CLKOUT_CMU_ACP_DIV_STAT 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8A04, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
DIV_STAT=[0]=o=
DIV_CLKOUT Status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.62 UFMC_CONFIG 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x8A10, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1]...

    Page 454

    Page 454 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-88 5.9.1.63 CLK_DIV_ISP0  Base Address: 0x1001_0000  Address = Base Address + 0xC300, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:7] –=Reserved=0x0= ISPDIV1_RATIO=[6:4]=RW=ACLK_DIV1=clock Divider Ratio= ACLK_DIV1== ACLK_ISP/(ISPDIV1_RATIO + 1)=0x0= RSVD=[3]=–=Reserved=0x0= ISPDIV0_RATIO=[2:0]=RW=ACLK_DIV0=clock Divider ratio= ACLK_DIV0== ACLK_ISP/(ISPDIV0_RATIO + 1)=0x0= = 5.9.1.64 CLK_DIV_ISP1  Base... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-88  
5.9.1.63 CLK_DIV_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC300, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0=
ISPDIV1_RATIO=[6:4]=RW=ACLK_DIV1=clock Divider Ratio=
ACLK_DIV1== ACLK_ISP/(ISPDIV1_RATIO + 1)=0x0=
RSVD=[3]=–=Reserved=0x0=
ISPDIV0_RATIO=[2:0]=RW=ACLK_DIV0=clock Divider ratio=
ACLK_DIV0== ACLK_ISP/(ISPDIV0_RATIO + 1)=0x0=
=
5.9.1.64 CLK_DIV_ISP1 
 Base...

    Page 455

    Page 455 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-89 5.9.1.66 CLK_DIV_STAT_ISP0  Base Address: 0x1001_0000  Address = Base Address + 0xC400, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:5] –=Reserved=0x0= DIV_ISPDIV1=[4]=o= DIV_ISPDIV1=status= 0 = Stable= 1 = Divider is changing= 0x0= RSVD=[3:1]=–=Reserved=0x0= DIV_ISPDIV0=[0]=o= DIV_ISPDIV0=status= 0 = Stable= 1 = Divider is changing= 0x0= = 5.9.1.67 CLK_DIV_STAT_ISP1  Base Address: 0x1001_0000  Address... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-89  
5.9.1.66 CLK_DIV_STAT_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC400, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_ISPDIV1=[4]=o=
DIV_ISPDIV1=status=
0 = Stable=
1 = Divider is changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_ISPDIV0=[0]=o=
DIV_ISPDIV0=status=
0 = Stable=
1 = Divider is changing=
0x0=
=
5.9.1.67 CLK_DIV_STAT_ISP1 
 Base Address: 0x1001_0000 
 Address...

    Page 456

    Page 456 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-90 5.9.1.69 CLK_GATE_IP_ISP0  Base Address: 0x1001_0000  Address = Base Address + 0xC800, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value CLK_UART_ISP [31] RW Gating all Clocks for UART_ISP 0 = Masks 1 = Passes 0x1 CLK_WDT_ISP [30] RW Gating all Clocks for WDT_ISP 0 = Masks 1 = Passes 0x1 RSVD [29] –=Reserved=0x1= CLK_PWM_ISm=[28]=RW= Gating all=Clocks for PWM_ISm= 0 = Masks= 1 = Passes= 0x1= CLK_MTCADC=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-90  
5.9.1.69 CLK_GATE_IP_ISP0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC800, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
CLK_UART_ISP [31] RW 
Gating all Clocks for UART_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_WDT_ISP [30] RW 
Gating all Clocks for WDT_ISP 
0 = Masks 
1 = Passes 
0x1 
RSVD [29] –=Reserved=0x1=
CLK_PWM_ISm=[28]=RW=
Gating all=Clocks for PWM_ISm=
0 = Masks=
1 = Passes=
0x1=
CLK_MTCADC=...

    Page 457

    Page 457 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-91 Name Bit Type Description Reset Value 0 = Masks 1 = Passes CLK_SMMU_DRC [9] RW Gating all Clocks for SMMU_DRC 0 = Masks 1 = Passes 0x1 CLK_SMMU_ISP [8] RW Gating all Clocks for SMMU_ISP 0 = Masks 1 = Passes 0x1 CLK_GICISP [7] RW Gating all Clocks for GICISP 0 = Masks 1 = Passes 0x1 CLK_ARM9S _MICE [6] RW Gating all Clocks for ARM9S_MICE 0 = Masks 1 = Passes 0x1 CLK_MCUISP [5] RW Gating all Clocks for MCUISP 0 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-91  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_SMMU_DRC [9] RW 
Gating all Clocks for SMMU_DRC 
0 = Masks 
1 = Passes 
0x1 
CLK_SMMU_ISP [8] RW 
Gating all Clocks for SMMU_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_GICISP [7] RW 
Gating all Clocks for GICISP 
0 = Masks 
1 = Passes 
0x1 
CLK_ARM9S 
_MICE [6] RW 
Gating all Clocks for ARM9S_MICE 
0 = Masks 
1 = Passes 
0x1 
CLK_MCUISP [5] RW 
Gating all Clocks for MCUISP 
0 =...

    Page 458

    Page 458 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-92 5.9.1.70 CLK_GATE_IP_ISP1  Base Address: 0x1001_0000  Address = Base Address + 0xC804, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:14] RW Reserved 0x3_FFFF CLK_SPI1_ISP [13] RW Gating all Clocks for SPI1_ISP 0 = Masks 1 = Passes 0x1 CLK_SPI0_ISP [12] RW Gating all Clocks for SPI0_ISP 0 = Masks 1 = Passes 0x1 RSVD [11:8] –=Reserved=0xc= CLK_SMMU3DNR=x7]=RW= Gating all=Clocks for=SMMU3DNR= 0 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-92  
5.9.1.70 CLK_GATE_IP_ISP1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC804, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:14] RW Reserved 0x3_FFFF 
CLK_SPI1_ISP [13] RW 
Gating all Clocks for SPI1_ISP 
0 = Masks 
1 = Passes 
0x1 
CLK_SPI0_ISP [12] RW 
Gating all Clocks for SPI0_ISP 
0 = Masks 
1 = Passes 
0x1 
RSVD [11:8] –=Reserved=0xc=
CLK_SMMU3DNR=x7]=RW=
Gating all=Clocks for=SMMU3DNR=
0 =...

    Page 459

    Page 459 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-93 5.9.1.71 CLK_GATE_SCLK_ISP  Base Address: 0x1001_0000  Address = Base Address + 0xC900, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:1] RW Reserved 0x7FFF_FFFF SCLK_MPWM_ISP [0] RW Gating Special Clocks for MPWM_ISP 0 = Masks 1 = Passes 0x1 5.9.1.72 MCUISP_PWR_CTRL  Base Address: 0x1001_0000  Address = Base Address + 0xC910, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-93  
5.9.1.71 CLK_GATE_SCLK_ISP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC900, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:1] RW Reserved 0x7FFF_FFFF 
SCLK_MPWM_ISP [0] RW 
Gating Special Clocks for MPWM_ISP 
0 = Masks 
1 = Passes 
0x1 
 
5.9.1.72 MCUISP_PWR_CTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xC910, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD...

    Page 460

    Page 460 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-94 5.9.1.73 CLKOUT_CMU_ISP  Base Address: 0x1001_0000  Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables= 0x1= RSVD=x15:14]=–=Reserved=0x0= DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0= RSVD=[7:5]=–=Reserved=0x0= MUX_SEi=[4:0]=RW= 00000 = ACLK_266 00001 = ACLK_DIV0 00010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-94  
5.9.1.73 CLKOUT_CMU_ISP 
 Base Address: 0x1001_0000 
 Address = Base Address + 0xCA00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = ACLK_266 
00001 = ACLK_DIV0 
00010 =...
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