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Samsung Exynos 5 User Manual

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    Page 501

    Page 501 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-135 5.9.1.114 CLK_DIV_TOP0  Base Address: 0x1002_0000  Address = Base Address + 0x0510, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ACLK_300_DISP1_ RATIl=x30:28]=RW= DIV_ACLK_300_DISP1=clock divider Ratio= ACLK_300_DISP1= = MOUT_ACLK_300_DISP1/(ACLK_300_DISP1_RA TIO + 1)= 0x0= RSVD=x27]=–=Reserved=0x0= ACLK_400_G3D_o ATIO=x26:24]=RW= DIV_ACLK_400_G3D=clock divider Ratio= ACLK_400_G3D= =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-135  
5.9.1.114 CLK_DIV_TOP0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0510, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_DISP1_
RATIl=x30:28]=RW=
DIV_ACLK_300_DISP1=clock divider Ratio=
ACLK_300_DISP1=
= 
MOUT_ACLK_300_DISP1/(ACLK_300_DISP1_RA
TIO + 1)=
0x0=
RSVD=x27]=–=Reserved=0x0=
ACLK_400_G3D_o
ATIO=x26:24]=RW=
DIV_ACLK_400_G3D=clock divider Ratio=
ACLK_400_G3D=
=...

    Page 502

    Page 502 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-136 5.9.1.115 CLK_DIV_TOP1  Base Address: 0x1002_0000  Address = Base Address + 0x0514, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ACLK_MIPI_HSf= _TXBASb_RATIO=x30:28]=RW= DIV_ACLK_MIPI_HSI_TXBASE=clock divider Ratio= ACLK_MIPI_HSI_TXBASE= = MOUT_ACLK_MIPI_HSI_TXBASE/= (ACLK_MIPI_HSI_TXBASE_RATIO + 1)= 0x0= RSVD=x27]=–=Reserved=0x0= ACLK_66_PRb= _RATIO=x26:24]=RW= DIV_ACLK_66_PRb=clock... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-136  
5.9.1.115 CLK_DIV_TOP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0514, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_MIPI_HSf=
_TXBASb_RATIO=x30:28]=RW=
DIV_ACLK_MIPI_HSI_TXBASE=clock divider Ratio=
ACLK_MIPI_HSI_TXBASE=
= MOUT_ACLK_MIPI_HSI_TXBASE/=
(ACLK_MIPI_HSI_TXBASE_RATIO + 1)=
0x0=
RSVD=x27]=–=Reserved=0x0=
ACLK_66_PRb=
_RATIO=x26:24]=RW=
DIV_ACLK_66_PRb=clock...

    Page 503

    Page 503 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-137 5.9.1.116 CLK_DIV_GSCL  Base Address: 0x1002_0000  Address = Base Address + 0x0520, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value GSCL_WRAP _B_RATIO [31:28] RW DIV_GSCL_WRAP_B clock divider Ratio SCLK_GSCL_WRAP_B = MOUT_GSCL_W RAP_B/ (GSCL_WRAP_B_RATIO + 1) 0x0 GSCL_WRAP _A_RATIO [27:24] RW DIV_GSCL_WRAP_A clock divider Ratio SCLK_GSCL_WRAP_A = MOUT_GSCL_W RAP_A/ (GSCL_WRAP_A_RATIO + 1) 0x0 RSVD... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-137  
5.9.1.116 CLK_DIV_GSCL 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0520, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GSCL_WRAP 
_B_RATIO [31:28] RW 
DIV_GSCL_WRAP_B clock divider Ratio 
SCLK_GSCL_WRAP_B 
= MOUT_GSCL_W RAP_B/ 
(GSCL_WRAP_B_RATIO + 1) 
0x0 
GSCL_WRAP 
_A_RATIO [27:24] RW 
DIV_GSCL_WRAP_A clock divider Ratio 
SCLK_GSCL_WRAP_A 
= MOUT_GSCL_W RAP_A/ 
(GSCL_WRAP_A_RATIO + 1) 
0x0 
RSVD...

    Page 504

    Page 504 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-138 5.9.1.117 CLK_DIV_DISP1_0  Base Address: 0x1002_0000  Address = Base Address + 0x052C, Reset Value = 0x0070_0000 Name Bit Type Description Reset Value HDMI_PIXEL _RATIO [31:28] RW DIV_HDMI_PIXEL clock divider Ratio SCLK_PIXEL = SCLK_VPLL/(HDMI_PIXEL_RATIO + 1) 0x0 DP1_EXT_MST _VID_RATIO [27:24] RW DIV_DP1_EXT_MST_VID clock divider Ratio SCLK_DP1_EXT_MST_VID = MOUT_DP1_EXT_MST_VID/ (DP1_EXT_MST_VID_RATIO + 1) 0x0... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-138  
5.9.1.117 CLK_DIV_DISP1_0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x052C, Reset Value = 0x0070_0000 
Name Bit Type Description Reset Value 
HDMI_PIXEL 
_RATIO [31:28] RW 
DIV_HDMI_PIXEL clock divider Ratio 
SCLK_PIXEL 
= SCLK_VPLL/(HDMI_PIXEL_RATIO + 1) 
0x0 
DP1_EXT_MST 
_VID_RATIO [27:24] RW 
DIV_DP1_EXT_MST_VID clock divider Ratio 
SCLK_DP1_EXT_MST_VID 
= MOUT_DP1_EXT_MST_VID/ 
(DP1_EXT_MST_VID_RATIO + 1) 
0x0...

    Page 505

    Page 505 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-139 5.9.1.118 CLK_DIV_GEN  Base Address: 0x1002_0000  Address = Base Address + 0x053C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] –=Reserved=0x0= JPEG_RATIO=x7:4]=RW= DIV_JPEG=clock divider Ratio= SCLK_JPEG= ==SCLK_CPLi/(JPEG_RATIO + 1)= 0x0= RSVD=[3:0]=–=Reserved=0x0= = 5.9.1.119 CLK_DIV_MAU  Base Address: 0x1002_0000  Address = Base Address + 0x0544, Reset Value = 0x0000_0000 Name Bit Type... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-139  
5.9.1.118 CLK_DIV_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x053C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x0=
JPEG_RATIO=x7:4]=RW=
DIV_JPEG=clock divider Ratio=
SCLK_JPEG=
==SCLK_CPLi/(JPEG_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.119 CLK_DIV_MAU 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0544, Reset Value = 0x0000_0000 
Name Bit Type...

    Page 506

    Page 506 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-140 5.9.1.120 CLK_DIV_FSYS0  Base Address: 0x1002_0000  Address = Base Address + 0x0548, Reset Value = 0x00B0_0000 Name Bit Type Description Reset Value RSVD [31:28] –=Reserved=0x0= USBDRD30_RATf l=[27:24]=RW= DIV_USBDRD30=clock divider Ratio= SCLK_USBDRD30= = MOUT_USBDRD30/(USBDRD30_RATIO + 1)= 0xB= SATA_RATIO=[23:20]=RW= DIV_SATA clock divider=oatio= SCLK_SATA= = MOUT_SATA/(SATA_RATIO + 1)= 0xB= RSVD=[19:0]=–=Reserved=0x0= = 5.9.1.121... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-140  
5.9.1.120 CLK_DIV_FSYS0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0548, Reset Value = 0x00B0_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
USBDRD30_RATf
l=[27:24]=RW=
DIV_USBDRD30=clock divider Ratio=
SCLK_USBDRD30=
= MOUT_USBDRD30/(USBDRD30_RATIO + 1)=
0xB=
SATA_RATIO=[23:20]=RW=
DIV_SATA clock divider=oatio=
SCLK_SATA=
= MOUT_SATA/(SATA_RATIO + 1)=
0xB=
RSVD=[19:0]=–=Reserved=0x0=
=
5.9.1.121...

    Page 507

    Page 507 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-141 5.9.1.122 CLK_DIV_FSYS2  Base Address: 0x1002_0000  Address = Base Address + 0x0550, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value MMC3_PRE _RATIO [31:24] RW DIV_MMC3_PRE clock divider Ratio SCLK_MMC3 = DOUT_MMC3/(MMC3_PRE_RATIO + 1) 0x0 RSVD [23:20] –=Reserved=0x0= MMC3_RATIO=[19:16]=RW= DIV_MMC3 clock divider Ratio= DOUT_MMC3= = MOUT_MMC3/(MMC3_RATIO + 1)= 0x0= MMC2_PRE= _RATIO=[15:8]=RW= DIV_MMC2_PRE=clock... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-141  
5.9.1.122 CLK_DIV_FSYS2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0550, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MMC3_PRE 
_RATIO [31:24] RW 
DIV_MMC3_PRE clock divider Ratio 
SCLK_MMC3 
= DOUT_MMC3/(MMC3_PRE_RATIO + 1) 
0x0 
RSVD [23:20] –=Reserved=0x0=
MMC3_RATIO=[19:16]=RW=
DIV_MMC3 clock divider Ratio=
DOUT_MMC3=
= MOUT_MMC3/(MMC3_RATIO + 1)=
0x0=
MMC2_PRE=
_RATIO=[15:8]=RW=
DIV_MMC2_PRE=clock...

    Page 508

    Page 508 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-142 5.9.1.123 CLK_DIV_PERIC0  Base Address: 0x1002_0000  Address = Base Address + 0x0558, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] –=Reserved=0x0= UART3_RATIl=[15:12]=RW= DIV_UART3 clock divider Ratio= SCLK_UART3= = MOUT_UART3/(UART3_RATIO + 1)= 0x0= UART2_RATIl=[11:8]=RW= DIV_UART2 clock divider Ratio= SCLK_UART2= = MOUT_UART2/(UART2_RATIO + 1)= 0x0= UART1_RATIl=[7:4]=RW= DIV_UART1 clock divider... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-142  
5.9.1.123 CLK_DIV_PERIC0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0558, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
UART3_RATIl=[15:12]=RW=
DIV_UART3 clock divider Ratio=
SCLK_UART3=
= MOUT_UART3/(UART3_RATIO + 1)=
0x0=
UART2_RATIl=[11:8]=RW=
DIV_UART2 clock divider Ratio=
SCLK_UART2=
= MOUT_UART2/(UART2_RATIO + 1)=
0x0=
UART1_RATIl=[7:4]=RW=
DIV_UART1 clock divider...

    Page 509

    Page 509 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-143 5.9.1.125 CLK_DIV_PERIC2  Base Address: 0x1002_0000  Address = Base Address + 0x0560, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] –=Reserved=0x0= SPI2_PRE_RATIO=[15:8]=RW= DIV_SPI2_PRE clock divider Ratio= SCLK_SPI2= = DOUT_SPI2/(SPI2_PRE_RATIO + 1)= 0x0= RSVD=[7:4]=–=Reserved=0x0= SPI2_RATIO=[3:0]=RW= DIV_SPI2 clock divider Ratio= DOUT_SPI2= = MOUT_SPI2/(SPI2_RATIO + 1)= 0x0= = 5.9.1.126... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-143  
5.9.1.125 CLK_DIV_PERIC2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0560, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
SPI2_PRE_RATIO=[15:8]=RW=
DIV_SPI2_PRE clock divider Ratio=
SCLK_SPI2=
= DOUT_SPI2/(SPI2_PRE_RATIO + 1)=
0x0=
RSVD=[7:4]=–=Reserved=0x0=
SPI2_RATIO=[3:0]=RW=
DIV_SPI2 clock divider Ratio=
DOUT_SPI2=
= MOUT_SPI2/(SPI2_RATIO + 1)=
0x0=
=
5.9.1.126...

    Page 510

    Page 510 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-144 5.9.1.127 CLK_DIV_PERIC5  Base Address: 0x1002_0000  Address = Base Address + 0x056C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:14] –=Reserved=0x0= I2S2_RATIO=[13:8]=RW= DIV_I2S2 clock divider Ratio= SCLK_I2S2= = SCLK_AUDIO2/(I2S2_RATIO + 1)= 0x0= RSVD=[7:6]=–=Reserved=0x0= I2S1_RATIO=[5:0]=RW= DIV_I2S1 clock divider Ratio= SCLK_I2S1= = SCLK_AUDIO1/(I2S1_RATIO + 1)= 0x0= = 5.9.1.128 SCLK_DIV_ISP ... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-144  
5.9.1.127 CLK_DIV_PERIC5 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x056C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:14] –=Reserved=0x0=
I2S2_RATIO=[13:8]=RW=
DIV_I2S2 clock divider Ratio=
SCLK_I2S2=
= SCLK_AUDIO2/(I2S2_RATIO + 1)=
0x0=
RSVD=[7:6]=–=Reserved=0x0=
I2S1_RATIO=[5:0]=RW=
DIV_I2S1 clock divider Ratio=
SCLK_I2S1=
= SCLK_AUDIO1/(I2S1_RATIO + 1)=
0x0=
=
5.9.1.128 SCLK_DIV_ISP 
...
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