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Samsung Exynos 5 User Manual

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Page 551

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-185  
5.9.1.188 BPLL_CON1 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0114, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector==
(only for monitoring)=
0 ==Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-low)=
0 ==Enables AFC=
1 = Disables AFC=
0x0=
FSEL=x19]=RW=
Monitoring=Frequency Select...

Page 552

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-186  
5.9.1.189 CLK_SRC_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0200, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:9] –=Reserved=0x0=
MUX_MCLK=
_DPHY_SEi=[8]=RW=
Control MUX_MCLK_DPHY=
0 = SCLK_MPLi=
1 = SCLK_BPLi=
0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_MCLK=
_CDREX_SEL=[4]=RW=
Control MUX_MCLK_CDREX=
0 = SCLK_MPLi=
1 = SCLK_BPLi=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
MUX_BPLL_SEL=x0]=RW=
Control...

Page 553

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-187  
5.9.1.190 CLK_MUX_STAT_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0400, Reset Value = 0x0011_1111 
Name Bit Type Description Reset Value 
RSVD [31:23] –=Reserved=0x0=
SCLK_MPLL_SEi=x22:20]=o=
Selection signal=(SCLK_MPLL) status of 
MUX_MPLL=
001== XXTI=
010 = MPLL_FOUT_RGT=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
MPLL_FOUT_SEi=x18:16]=o=
Selection signal status of=MUX_MPLL_FOUT=
001 = MPLL_FOUT_800=
010 =...

Page 554

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-188  
5.9.1.191 CLK_DIV_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[30:28]=RW=
DIs_MCLK_CDREX2 clock divider=oatio=
MCLK_CDREX2== 
MOUT_MCLK_CDREX/(MCLK_CDREX2_RATIl=+=
1)=
0x0=
RSVD=[27]=–=Reserved=0x0=
ACLK_SFRTZASC
P_RATIl=[26:24]=RW=
DIs_ACLK_SFRTZASCP clock divider oatio=
ACLK_SFRTZASCP==...

Page 555

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-189  
5.9.1.192 CLK_DIV_STAT_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
DIV_MCLK=
_CDREX2=[28]=o=
DIs_MCLK_CDREX2=status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[27:25]=–=Reserved=0x0=
DIV_ACLK=
_SFRTZASCP=[24]=o=
DIs_ACLK_SFRTZASCP status=
0== Stable=
1 = Divider is changing=
0x0=
RSVD=[23:21]=–=Reserved=0x0=...

Page 556

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-190  
5.9.1.193 CLK_GATE_IP_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0900, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x3F=
CLK_TZASC=
_CBXt=[25]=RW=
Gating AXI=Clock for TZASC_XCBXW and DRAM 
controller port1=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_CBXo=[24]=RW=
Gating AXI=Clock for TZASC_XCBXR=
0== Masks=
1 = Passes=
0x1=
CLK_TZASC=
_DRBXW=[23]=RW=
Gating AXI=Clock for...

Page 557

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-191  
Name Bit Type Description Reset Value 
CLK_DREX2 [3] RW 
Gating all Clocks for DRAM controller and clk2x for 
LPDDRHPHY0 and LPDDRHPHY1 
0 = Masks 
1 = Passes 
0x1 
CLK 
_SFRCDREXP [2] RW 
Gating all Clocks for AHB2APB_CDREXP and 
ASYNCAHBM_PCX_CDREXP 
0 = Masks 
1 = Passes 
0x1 
RSVD [1:0] – Reserved 0x3

Page 558

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-192  
5.9.1.194 DMC_FREQ_CTRL 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0914, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:15] –=Reserved=0x0=
MCLK_CDREX2=
_RATIO=[14:12]=RW=
DIV_MCLK_CDREX2 clock divider oatio=
MCLK_CDREX2 = MOUT_MCLK_DPHY/==
(MCLK_CDREX2_RATIO + 1)=
0x0=
RSVD=[11]=–=Reserved=0x0=
MCLK_DPHY=
_RATIO=[10:8]=RW=
DIV_MCLK_DPHY clock divider oatio=
MCLK_DPHY = MOUT_MCLK_DPHY/==...

Page 559

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-193  
5.9.1.196 CLKOUT_CMU_CDREX 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = MCLK_CDREX=
00001 = ACLK_CDREX=
00010...

Page 560

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-194  
5.9.1.199 LPDDR3PHY_CON3 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0A20, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
DRAM_POP_EN [31] RW Set this bit to 1 for POP 0x0 
RSVD [30:0] –=Reserved=0x0=
=
5.9.1.200 PLL_DIV2_SEL 
 Base Address: 0x1003_0000 
 Address = Base Address + 0x0A24, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
MPLL_FOUT_SEi=x4]=RW=...

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