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Samsung Exynos 5 User Manual

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    Page 531

    Page 531 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-165 5.9.1.158 CLK_GATE_IP_DISP1  Base Address: 0x1002_0000  Address = Base Address + 0x0928, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:10] –=Reserved=0x3F_FFFc= CLK_SMMUTVu=x9]=RW= Gating all=Clocks for=SMMUTVu= 0 = Masks= 1 = Passes= 0x1= CLh= _SMMUFIMD1u=x8]=RW= Gating all=Clocks for=SMMUFIMD1X= 0 = Masks= 1 = Passes= 0x1= CLK_ASYNCTVX=[7]=RW= Gating all=Clocks for ASYNCTVX= 0: Masks= 1: Passes= 0x1=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-165  
5.9.1.158 CLK_GATE_IP_DISP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0928, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0x3F_FFFc=
CLK_SMMUTVu=x9]=RW=
Gating all=Clocks for=SMMUTVu=
0 = Masks=
1 = Passes=
0x1=
CLh=
_SMMUFIMD1u=x8]=RW=
Gating all=Clocks for=SMMUFIMD1X=
0 = Masks=
1 = Passes=
0x1=
CLK_ASYNCTVX=[7]=RW=
Gating all=Clocks for ASYNCTVX=
0: Masks=
1: Passes=
0x1=...

    Page 532

    Page 532 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-166 5.9.1.159 CLK_GATE_IP_MFC  Base Address: 0x1002_0000  Address = Base Address + 0x092C, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:3] –=Reserved=0x1FFF_FFFc= CLK_SMMUMFCR=[2]=RW= Gating all=Clocks for=SMMUMFCR= 0 = Masks= 1 = Passes= 0x1= CLK_SMMUMFCL=[1]=RW= Gating all=Clocks for=SMMUMFCL= 0 = Masks= 1 = Passes= 0x1= CLK_MFC=[0]=RW= Gating all=Clocks for=MFC= 0 = Masks= 1 = Passes= 0x1= = 5.9.1.160... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-166  
5.9.1.159 CLK_GATE_IP_MFC 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x092C, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:3] –=Reserved=0x1FFF_FFFc=
CLK_SMMUMFCR=[2]=RW=
Gating all=Clocks for=SMMUMFCR=
0 = Masks=
1 = Passes=
0x1=
CLK_SMMUMFCL=[1]=RW=
Gating all=Clocks for=SMMUMFCL=
0 = Masks=
1 = Passes=
0x1=
CLK_MFC=[0]=RW=
Gating all=Clocks for=MFC=
0 = Masks=
1 = Passes=
0x1=
=
5.9.1.160...

    Page 533

    Page 533 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-167 5.9.1.161 CLK_GATE_IP_GEN  Base Address: 0x1002_0000  Address = Base Address + 0x0934, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:10] –=Reserved=0x3F_FFFc= CLh= _SMMUMDMA1=x9]=RW= Gating all=Clocks for=SMMUMDMA1= 0 = Masks= 1 = Passes= 0x1= RSVD=x8]=–=Reserved=0x1= CLK_SMMUJPEG=x7]=RW= Gating all=Clocks for=SMMUJPEG= 0 = Masks= 1 = Passes= 0x1= CLh= _SMMUROTATOo=xS]=RW= Gating all=Clocks... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-167  
5.9.1.161 CLK_GATE_IP_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0934, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:10] –=Reserved=0x3F_FFFc=
CLh=
_SMMUMDMA1=x9]=RW=
Gating all=Clocks for=SMMUMDMA1=
0 = Masks=
1 = Passes=
0x1=
RSVD=x8]=–=Reserved=0x1=
CLK_SMMUJPEG=x7]=RW=
Gating all=Clocks for=SMMUJPEG=
0 = Masks=
1 = Passes=
0x1=
CLh=
_SMMUROTATOo=xS]=RW=
Gating all=Clocks...

    Page 534

    Page 534 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-168 5.9.1.162 CLK_GATE_IP_FSYS  Base Address: 0x1002_0000  Address = Base Address + 0x0944, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:31] –=Reserved=0x1FFF= CLK_WDT_IOm=x30]=RW= Gating all=Clocks for=WDT_IOm= 0 = Masks= 1 = Passes= 0x1= RSVD=x29:27]=–=Reserved=0x7= CLh_SMMUMCU= _IOP=x26]=RW= Gating all=Clocks for=SMMUMCU_ISm= 0 = Masks= 1 = Passes= 0x1= CLK_SATA_PHY= _I2C=x25]=RW= Gating all=Clocks... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-168  
5.9.1.162 CLK_GATE_IP_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0944, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:31] –=Reserved=0x1FFF=
CLK_WDT_IOm=x30]=RW=
Gating all=Clocks for=WDT_IOm=
0 = Masks=
1 = Passes=
0x1=
RSVD=x29:27]=–=Reserved=0x7=
CLh_SMMUMCU=
_IOP=x26]=RW=
Gating all=Clocks for=SMMUMCU_ISm=
0 = Masks=
1 = Passes=
0x1=
CLK_SATA_PHY=
_I2C=x25]=RW=
Gating all=Clocks...

    Page 535

    Page 535 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-169 Name Bit Type Description Reset Value CLK_SDMMC0 [12] RW Gating all clocks for SDMMC0 0 = Masks 1 = Passes 0x1 CLK_SMMURTIC [11] RW Gating all Clocks for SMMURTIC 0 = Masks 1 = Passes 0x1 RSVD [10] – Reserved 0x1 CLK_RTIC [9] RW Gating all Clocks for RTIC 0 = Masks 1 = Passes 0x1 CLK_MIPI_HSI [8] RW Gating all Clocks for MIPI_HSI 0 = Masks 1 = Passes 0x1 CLK_USBOTG [7] RW Gating all Clocks for USBOTG 0 = Masks 1 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-169  
Name Bit Type Description Reset Value 
CLK_SDMMC0 [12] RW 
Gating all clocks for SDMMC0 
0 = Masks 
1 = Passes 
0x1 
CLK_SMMURTIC [11] RW 
Gating all Clocks for SMMURTIC 
0 = Masks 
1 = Passes 
0x1 
RSVD [10] – Reserved 0x1 
CLK_RTIC [9] RW 
Gating all Clocks for RTIC 
0 = Masks 
1 = Passes 
0x1 
CLK_MIPI_HSI [8] RW 
Gating all Clocks for MIPI_HSI 
0 = Masks 
1 = Passes 
0x1 
CLK_USBOTG [7] RW 
Gating all Clocks for USBOTG 
0 = Masks 
1 =...

    Page 536

    Page 536 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-170 5.9.1.163 CLK_GATE_IP_PERIC  Base Address: 0x1002_0000  Address = Base Address + 0x0950, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value CLK_HS-I2C3 [31] RW Gating all Clocks for HS-I2C3 0 = Masks 1 = Passes 0x1 CLK_HS-I2C2 [30] RW Gating all Clocks for HS-I2C2 0 = Masks 1 = Passes 0x1 CLK_HS-I2C1 [29] RW Gating all Clocks for HS-I2C1 0 = Masks 1 = Passes 0x1 CLK_HS-I2C0 [28] RW Gating all Clocks for... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-170  
5.9.1.163 CLK_GATE_IP_PERIC 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0950, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
CLK_HS-I2C3 [31] RW 
Gating all Clocks for HS-I2C3 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C2 [30] RW 
Gating all Clocks for HS-I2C2 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C1 [29] RW 
Gating all Clocks for HS-I2C1 
0 = Masks 
1 = Passes 
0x1 
CLK_HS-I2C0 [28] RW 
Gating all Clocks for...

    Page 537

    Page 537 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-171 Name Bit Type Description Reset Value 0 = Masks 1 = Passes CLK_SPI0 [16] RW Gating all Clocks for SPI0 0 = Masks 1 = Passes 0x1 CLK_ADC [15] RW Gating all Clocks for ADC 0 = Masks 1 = Passes 0x1 CLK_I2CHDMI [14] RW Gating all Clocks for I2CHDMI 0 = Masks 1 = Passes 0x1 CLK_I2C7 [13] RW Gating all Clocks for I2C7 0 = Masks 1 = Passes 0x1 CLK_I2C6 [12] RW Gating all Clocks for I2C6 0 = Masks 1 = Passes 0x1... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-171  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_SPI0 [16] RW 
Gating all Clocks for SPI0 
0 = Masks 
1 = Passes 
0x1 
CLK_ADC [15] RW 
Gating all Clocks for ADC 
0 = Masks 
1 = Passes 
0x1 
CLK_I2CHDMI [14] RW 
Gating all Clocks for I2CHDMI 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C7 [13] RW 
Gating all Clocks for I2C7 
0 = Masks 
1 = Passes 
0x1 
CLK_I2C6 [12] RW 
Gating all Clocks for I2C6 
0 = Masks 
1 = Passes 
0x1...

    Page 538

    Page 538 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-172 Name Bit Type Description Reset Value 0 = Masks 1 = Passes CLK_UART0 [0] RW Gating all Clocks for UART0 0 = Masks 1 = Passes 0x1 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-172  
Name Bit Type Description Reset Value 
0 = Masks 
1 = Passes 
CLK_UART0 [0] RW 
Gating all Clocks for UART0 
0 = Masks 
1 = Passes 
0x1

    Page 539

    Page 539 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-173 5.9.1.164 CLK_GATE_IP_PERIS  Base Address: 0x1002_0000  Address = Base Address + 0x0960, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:25] –=Reserved=0x3FFc= CLK_MONOCNT=x24]=RW= Gating all Clocks for Monotonic Counter= 0 = Masks= 1 = Passes= 0x1= CLK_PKEY1=x23]=RW= Gating all Clocks for Provision key 1= 0 = Masks= 1 = Passes= 0x1= CLK_PKEY0=x22]=RW= Gating all Clocks for Provision key 0= 0 = Masks= 1 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-173  
5.9.1.164 CLK_GATE_IP_PERIS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0960, Reset Value = 0xFFFF_FFFF 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x3FFc=
CLK_MONOCNT=x24]=RW=
Gating all Clocks for Monotonic Counter=
0 = Masks=
1 = Passes=
0x1=
CLK_PKEY1=x23]=RW=
Gating all Clocks for Provision key 1=
0 = Masks=
1 = Passes=
0x1=
CLK_PKEY0=x22]=RW=
Gating all Clocks for Provision key 0=
0 = Masks=
1 =...

    Page 540

    Page 540 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-174 Name Bit Type Description Reset Value 1 = Passes CLK_TZPC5 [11] RW Gating all clocks for TZPC5 0 = Masks 1 = Passes 0x1 CLK_TZPC4 [10] RW Gating all Clocks for TZPC4 0 = Masks 1 = Passes 0x1 CLK_TZPC3 [9] RW Gating all Clocks for TZPC3 0 = Masks 1 = Passes 0x1 CLK_TZPC2 [8] RW Gating all Clocks for TZPC2 0 = Masks 1 = Passes 0x1 CLK_TZPC1 [7] RW Gating all Clocks for TZPC1 0 = Masks 1 = Passes 0x1 CLK_TZPC0 [6]... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-174  
Name Bit Type Description Reset Value 
1 = Passes 
CLK_TZPC5 [11] RW 
Gating all clocks for TZPC5 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC4 [10] RW 
Gating all Clocks for TZPC4 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC3 [9] RW 
Gating all Clocks for TZPC3 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC2 [8] RW 
Gating all Clocks for TZPC2 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC1 [7] RW 
Gating all Clocks for TZPC1 
0 = Masks 
1 = Passes 
0x1 
CLK_TZPC0 [6]...
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