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Samsung Exynos 5 User Manual

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    Page 481

    Page 481 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-115 5.9.1.96 CLK_SRC_FSYS  Base Address: 0x1002_0000  Address = Base Address + 0x0244, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:29] –=Reserved=0x0= USBDRD30_SEL=[28]=RW= Control MUX_USBDRD30, the source clock of USBDRD30= 0 = SCLK_MPLL_USER= 1 = SCLK_CPLi= 0x0= RSVD=[27:25]=–=Reserved=0x0= SATA_SEL=[24]=RW= Control MUX_SATA, the source clock of SATA= 0 = SCLK_MPLL_USER= 1 = SCLK_BPLi_USEo= 0x0=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-115  
5.9.1.96 CLK_SRC_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0244, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
USBDRD30_SEL=[28]=RW=
Control MUX_USBDRD30, the source clock of 
USBDRD30=
0 = SCLK_MPLL_USER=
1 = SCLK_CPLi=
0x0=
RSVD=[27:25]=–=Reserved=0x0=
SATA_SEL=[24]=RW=
Control MUX_SATA, the source clock of SATA=
0 = SCLK_MPLL_USER=
1 = SCLK_BPLi_USEo=
0x0=...

    Page 482

    Page 482 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-116 Name Bit Type Description Reset Value 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved MMC0_SEL [3:0] RW Control MUX_MMC0, the source clock of MMC0 0000 = XXTI 0001 = SCLK_GPLL 0010 = SCLK_HDMI24M 0011 = SCLK_DPTXPHY 0100 = SCLK_USBHOST20PHY 0101 = SCLK_HDMIPHY 0110 = SCLK_MPLL_USER 0111 = SCLK_BPLL_USER 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved 0x0 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-116  
Name Bit Type Description Reset Value 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
MMC0_SEL [3:0] RW 
Control MUX_MMC0, the source clock of MMC0 
0000 = XXTI 
0001 = SCLK_GPLL 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_BPLL_USER 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x0

    Page 483

    Page 483 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-117 5.9.1.97 CLK_SRC_GEN  Base Address: 0x1002_0000  Address = Base Address + 0x0248, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] –=Reserved=0x0= JPEG_SEL=x3:0]=RW= Control MUX_JPEG, the source clock of JPEG= 0000 = XXTf= 0001 = XXTf= 0010 = SCLK_HDMI24M= 0011 = SCLK_DPTXPHY= 0100 = SCLK_USBHOST20PHY= 0101 = SCLK_HDMIPHY= 0110 = SCLK_MPLL_USEo= 0111 = SCLK_EPLL= 1000 = SCLK_VPLL= 1001== SCLK_CPLi= Others... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-117  
5.9.1.97 CLK_SRC_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0248, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0x0=
JPEG_SEL=x3:0]=RW=
Control MUX_JPEG, the source clock of JPEG=
0000 = XXTf=
0001 = XXTf=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=
Others...

    Page 484

    Page 484 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-118 5.9.1.98 CLK_SRC_PERIC0  Base Address: 0x1002_0000  Address = Base Address + 0x0250, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:28] –=Reserved=0x0= PW M_SEL=x27:24]=RW= Control MUX_PWM, the source clock of PWM= 0000 = XXTf= 0001 = XXTI= 0010 = SCLK_HDMI24M= 0011 = SCLK_DPTXPHY= 0100 = SCLK_USBHOST20PHY= 0101 = SCLK_HDMIPHY= 0110 ==SCLK_MPLL_USER= 0111 = SCLK_EPLL= 1000 = SCLK_VPLL= 1001== SCLK_CPLi=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-118  
5.9.1.98 CLK_SRC_PERIC0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0250, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
PW M_SEL=x27:24]=RW=
Control MUX_PWM, the source clock of PWM=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 ==SCLK_MPLL_USER=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=...

    Page 485

    Page 485 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-119 Name Bit Type Description Reset Value 0101 = SCLK_HDMIPHY 0110 = SCLK_MPLL_USER 0111 = SCLK_EPLL 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved UART0_SEL [3:0] RW Control MUX_UART0, the source clock of UART0 0000 = XXTI 0001 = XXTI 0010 = SCLK_HDMI24M 0011 = SCLK_DPTXPHY 0100 = SCLK_USBHOST20PHY 0101 = SCLK_HDMIPHY 0110 = SCLK_MPLL_USER 0111 = SCLK_EPLL 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved 0x0 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-119  
Name Bit Type Description Reset Value 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
UART0_SEL [3:0] RW 
Control MUX_UART0, the source clock of UART0 
0000 = XXTI 
0001 = XXTI 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x0

    Page 486

    Page 486 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-120 5.9.1.99 CLK_SRC_PERIC1  Base Address: 0x1002_0000  Address = Base Address + 0x0254, Reset Value = 0x0000_0011 Name Bit Type Description Reset Value RSVD [31:28] –=Reserved=0x0= SPI2_SEL=[27:24]=RW= Control MUX_SPI2, the source clock of SPI2= 0000 = XXTf= 0001 = XXTI= 0010 = SCLK_HDMI24M= 0011 = SCLK_DPTXPHY= 0100 = SCLK_USBHOST20PHY= 0101 = SCLK_HDMIPHY= 0110 = SCLK_MPLL_USEo= 0111 = SCLK_EPLL= 1000 = SCLK_VPLL= 1001== SCLK_CPLi=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-120  
5.9.1.99 CLK_SRC_PERIC1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0254, Reset Value = 0x0000_0011 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
SPI2_SEL=[27:24]=RW=
Control MUX_SPI2, the source clock of SPI2=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=...

    Page 487

    Page 487 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-121 Name Bit Type Description Reset Value AUDIO2_SEL [7:4] RW Control MUX_AUDIO2, the source clock of AUDIO2 0000 = AUDIOCDCLK2 0001 = XXTI 0010 = SCLK_HDMI24M 0011 = SCLK_DPTXPHY 0100 = SCLK_UHOST20PHY 0101 = SCLK_HDMIPHY 0110 = SCLK_MPLL_USER 0111 = SCLK_EPLL 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved 0x1 AUDIO1_SEL [3:0] RW Control MUX_AUDIO1, the source clock of AUDIO1 0000 = AUDIOCDCLK1 0001 = XXTI 0010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-121  
Name Bit Type Description Reset Value 
AUDIO2_SEL [7:4] RW 
Control MUX_AUDIO2, the source clock of 
AUDIO2 
0000 = AUDIOCDCLK2 
0001 = XXTI 
0010 = SCLK_HDMI24M 
0011 = SCLK_DPTXPHY 
0100 = SCLK_UHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved 
0x1 
AUDIO1_SEL [3:0] RW 
Control MUX_AUDIO1, the source clock of 
AUDIO1 
0000 = AUDIOCDCLK1 
0001 = XXTI 
0010 =...

    Page 488

    Page 488 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-122 5.9.1.100 SCLK_SRC_ISP  Base Address: 0x1002_0000  Address = Base Address + 0x0270, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] –=Reserved=0x0= PW M_ISm_SEL=x15:12]=RW= Control MUX_PWM_ISm, the source clock of PW M_ISm= 0000 = XXTf= 0001 = XXTI= 0010 = SCLK_HDMI24M= 0011 = SCLK_DPTXPHY= 0100 = SCLK_USBHOST20PHY= 0101 = SCLK_HDMIPHY= 0110 = SCLK_MPLL_USEo= 0111 = SCLK_EPLL= 1000 = SCLK_VPLL= 1001==... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-122  
5.9.1.100 SCLK_SRC_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0270, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
PW M_ISm_SEL=x15:12]=RW=
Control MUX_PWM_ISm, the source clock of 
PW M_ISm=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001==...

    Page 489

    Page 489 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-123 Name Bit Type Description Reset Value 0100 = SCLK_USBHOST20PHY 0101 = SCLK_HDMIPHY 0110 = SCLK_MPLL_USER 0111 = SCLK_EPLL 1000 = SCLK_VPLL 1001 = SCLK_CPLL Others = Reserved 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-123  
Name Bit Type Description Reset Value 
0100 = SCLK_USBHOST20PHY 
0101 = SCLK_HDMIPHY 
0110 = SCLK_MPLL_USER 
0111 = SCLK_EPLL 
1000 = SCLK_VPLL 
1001 = SCLK_CPLL 
Others = Reserved

    Page 490

    Page 490 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-124 5.9.1.101 CLK_SRC_MASK_TOP  Base Address: 0x1002_0000  Address = Base Address + 0x0310, Reset Value = 0x0000_0001 Name Bit Type Description Reset Value RSVD [31:1] –=Reserved=0x0= VPLLSRC_MASK=[0]=RW= Masks output clock of MUX_VPLLSRC= 0 = Masks= 1 = Unmasks= 0x1= = 5.9.1.102 CLK_SRC_MASK_GSCL  Base Address: 0x1002_0000  Address = Base Address + 0x0320, Reset Value = 0x1111_0000 Name Bit Type Description Reset Value RSVD... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-124  
5.9.1.101 CLK_SRC_MASK_TOP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0310, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
VPLLSRC_MASK=[0]=RW=
Masks output clock of MUX_VPLLSRC=
0 = Masks=
1 = Unmasks=
0x1=
=
5.9.1.102 CLK_SRC_MASK_GSCL 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0320, Reset Value = 0x1111_0000 
Name Bit Type Description Reset Value 
RSVD...
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