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Samsung Exynos 5 User Manual

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    Page 421

    Page 421 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-55 5.9.1.8 CLK_DIV_STAT_CPU0  Base Address: 0x1001_0000  Address = Base Address + 0x0600, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:29] –=Reserved=0x0= DIV_ARM2=[28]=o= DIV_ARM2=status= 0 = Stable= 1 = Divider is=on changing= 0x0= RSVD=x27:25]=–=Reserved=0x0= DIV_APLL=[24]=o= DIV_APLL status= 0 = Stable= 1 = Divider is=on changing= 0x0= RSVD=[23:21]=–=Reserved=0x0= DIV_PCLK_DBG=[20]=o= DIV_PCLK_DBG... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-55  
5.9.1.8 CLK_DIV_STAT_CPU0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0600, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
DIV_ARM2=[28]=o=
DIV_ARM2=status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=x27:25]=–=Reserved=0x0=
DIV_APLL=[24]=o=
DIV_APLL status=
0 = Stable=
1 = Divider is=on changing=
0x0=
RSVD=[23:21]=–=Reserved=0x0=
DIV_PCLK_DBG=[20]=o=
DIV_PCLK_DBG...

    Page 422

    Page 422 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-56 5.9.1.9 CLK_DIV_STAT_CPU1  Base Address: 0x1001_0000  Address = 0x1004_4604, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:5] –=Reserved=0x0= DIV_HPM=[4]=o= DIV_HPM status= 0== Stable= 1 = Divider is on changing= 0x0= RSVD=[3:1]=–=Reserved=0x0= DIV_COPY=[0]=o= DIV_COPY status= 0 = Stable= 1 = Divider is=on changing= 0x0= = 5.9.1.10 CLK_GATE_SCLK_CPU  Base Address: 0x1001_0000  Address = Base Address +... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-56  
5.9.1.9 CLK_DIV_STAT_CPU1 
 Base Address: 0x1001_0000 
 Address = 0x1004_4604, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5] –=Reserved=0x0=
DIV_HPM=[4]=o=
DIV_HPM status=
0== Stable=
1 = Divider is on changing=
0x0=
RSVD=[3:1]=–=Reserved=0x0=
DIV_COPY=[0]=o=
DIV_COPY status=
0 = Stable=
1 = Divider is=on changing=
0x0=
=
5.9.1.10 CLK_GATE_SCLK_CPU 
 Base Address: 0x1001_0000 
 Address = Base Address +...

    Page 423

    Page 423 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-57 5.9.1.11 CLKOUT_CMU_CPU  Base Address: 0x1001_0000  Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 Name Bit Type Description Reset Value RSVD [31:17] –=Reserved=0x0= ENB_CLKOUT=[16]=RW= Enable CLKOUT= 0 = Disables= 1 = Enables= 0x1= RSVD=x15:14]=–=Reserved=0x0= DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0= RSVD=[7:5]=–=Reserved=0x0= MUX_SEi=[4:0]=RW= 00000 = APLL_FOUT= 00001 = Reserved= 00010 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-57  
5.9.1.11 CLKOUT_CMU_CPU 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0A00, Reset Value = 0x0001_0000 
Name Bit Type Description Reset Value 
RSVD [31:17] –=Reserved=0x0=
ENB_CLKOUT=[16]=RW=
Enable CLKOUT=
0 = Disables=
1 = Enables=
0x1=
RSVD=x15:14]=–=Reserved=0x0=
DIV_RATIl=[13:8]=RW=Divide=Ratio (Divide Ratio = DIV_RATIO + 1)=0x0=
RSVD=[7:5]=–=Reserved=0x0=
MUX_SEi=[4:0]=RW=
00000 = APLL_FOUT=
00001 = Reserved=
00010 =...

    Page 424

    Page 424 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-58 5.9.1.13 ARMCLK_STOPCTRL  Base Address: 0x1001_0000  Address = Base Address + 0x1000, Reset Value = 0x0000_0044 Name Bit Type Description Reset Value RSVD [31:8] –=Reserved=0x0= POST_W AIT_CNT=x7:4]=RW= Clock freeze cycle after ARM clamp=(CLADUAL- CORE0,=CLADUAi-CORE1,=CLADUAi- COREOUT,=CLAMPL2_0,=CLAMPL2_1) or reset signal=(nCPURESET,=nDBGRESET,=nSCURESET,= L2nRESET,=nWDRESET,=nPERIPHRESET,= nPTMRESET) transition= 0x4= PRE_t... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-58  
5.9.1.13 ARMCLK_STOPCTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1000, Reset Value = 0x0000_0044 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x0=
POST_W AIT_CNT=x7:4]=RW=
Clock freeze cycle after ARM clamp=(CLADUAL-
CORE0,=CLADUAi-CORE1,=CLADUAi-
COREOUT,=CLAMPL2_0,=CLAMPL2_1) or reset 
signal=(nCPURESET,=nDBGRESET,=nSCURESET,=
L2nRESET,=nWDRESET,=nPERIPHRESET,=
nPTMRESET) transition=
0x4=
PRE_t...

    Page 425

    Page 425 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-59 5.9.1.14 PARITYFAIL_STATUS  Base Address: 0x1001_0000  Address = Base Address + 0x1010, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:18] –=Reserved=0x0= PARITYFAILSCr=[17:16]=o= Parity output pin from SCU tag RAMs = OR=operated=output from each E4D processor= present in the design= 0x0= PARITYFAIL1=[15:8]=o= Parity output pin from the RAM array for CPU1= Indicates a parity fail= 0 = No parity fail= 1 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-59  
5.9.1.14 PARITYFAIL_STATUS 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1010, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:18] –=Reserved=0x0=
PARITYFAILSCr=[17:16]=o=
Parity output pin from SCU tag RAMs =
OR=operated=output from each E4D processor=
present in the design=
0x0=
PARITYFAIL1=[15:8]=o=
Parity output pin from the RAM array for CPU1=
Indicates a parity fail=
0 = No parity fail=
1 =...

    Page 426

    Page 426 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-60 5.9.1.15 PARITYFAIL_CLEAR  Base Address: 0x1001_0000  Address = Base Address + 0x1014, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:18] –=Reserved=0x0= PARITYFAILSCr=[17:16]=RWu= Parity output pin from SCU tag RAMs = OR=operated output from each E4D processor present in the design= 0x0= PARITYFAIL1=[15:8]=RWu= Parity output pin from the RAM array for CPU1= Indicates a Parity Fail= 0== No parity fail= 1 =... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-60  
5.9.1.15 PARITYFAIL_CLEAR 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1014, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:18] –=Reserved=0x0=
PARITYFAILSCr=[17:16]=RWu=
Parity output pin from SCU tag RAMs =
OR=operated output from each E4D processor 
present in the design=
0x0=
PARITYFAIL1=[15:8]=RWu=
Parity output pin from the RAM array for CPU1=
Indicates a Parity Fail=
0== No parity fail=
1 =...

    Page 427

    Page 427 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-61 5.9.1.16 PWR_CTRL  Base Address: 0x1001_0000  Address = Base Address + 0x1020, Reset Value = 0x0000_0033 Name Bit Type Description Reset Value RSVD [31] –=Reserved=0x0= ARM2_RATIO=x30:28]=RW=DIV_ARM2 clock divider=oatio when ARM cores are in W ait For Interrupt/Event state=0x0= RSVD=x27:21]=–=Reserved=0x0= CSCLK_AUTO= _ENB_IN_DEBUd=x20]=RW= Force CoreSight clocks to toggle when debugger= is attached= 0 = Disables= 1 = Enables= 0x0=... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-61  
5.9.1.16 PWR_CTRL 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1020, Reset Value = 0x0000_0033 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ARM2_RATIO=x30:28]=RW=DIV_ARM2 clock divider=oatio when ARM cores 
are in W ait For Interrupt/Event state=0x0=
RSVD=x27:21]=–=Reserved=0x0=
CSCLK_AUTO=
_ENB_IN_DEBUd=x20]=RW=
Force CoreSight clocks to toggle when debugger=
is attached=
0 = Disables=
1 = Enables=
0x0=...

    Page 428

    Page 428 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-62 5.9.1.17 PWR_CTRL2  Base Address: 0x1001_0000  Address = Base Address + 0x1024, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:26] –=Reserved=0x0= DIs_ARM2_UP= _ENB=x25]=RW= Enable ARMCLK up feature with ARM cores when= exiting from IDLE mode for DIV_ARM2= 0 = Disables= 1 = Enables= 0x0= DIs_ARM_UP_EN B=x24]=RW= Enable ARMCLK up feature with ARM cores when= exiting from IDLE mode for DIV_ARM= 0 = Disables= 1... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-62  
5.9.1.17 PWR_CTRL2 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1024, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
DIs_ARM2_UP=
_ENB=x25]=RW=
Enable ARMCLK up feature with ARM cores when=
exiting from IDLE mode for DIV_ARM2=
0 = Disables=
1 = Enables=
0x0=
DIs_ARM_UP_EN
B=x24]=RW=
Enable ARMCLK up feature with ARM cores when=
exiting from IDLE mode for DIV_ARM=
0 = Disables=
1...

    Page 429

    Page 429 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-63 5.9.1.18 APLL_CON0_L8  Base Address: 0x1001_0000  Address = Base Address + 0x1100, Reset Value = 0x00C8_0301 Name Bit Type Description Reset Value RSVD [31:28] –=Reserved=0x0= FSEL=[27]=RW=APLL FSEL value=0x0= RSVD=[26]=–=Reserved=0x0= MDIV=[25:16]=RW=APLL M=Divide Value=0xC8= RSVD=[15:14]=–=Reserved=0x0= PDIV=[13:8]=RW=APLL P=Divide Value=0x3= RSVD=[7:3]=–=Reserved=0x0= SDIV=[2:0]=RW=APLL S=Divide Value=0x1= = 5.9.1.19 APLL_CON0_L7... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-63  
5.9.1.18 APLL_CON0_L8 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1100, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.19 APLL_CON0_L7...

    Page 430

    Page 430 Samsung Confidential Exynos 5250_UM 5 Clock Controller 5-64 5.9.1.20 APLL_CON0_L6  Base Address: 0x1001_0000  Address = Base Address + 0x1108, Reset Value = 0x00C8_0301 Name Bit Type Description Reset Value RSVD [31:28] –=Reserved=0x0= FSEL=[27]=RW=APLL FSEL value=0x0= RSVD=[26]=–=Reserved=0x0= MDIV=[25:16]=RW=APLL M=Divide Value=0xC8= RSVD=[15:14]=–=Reserved=0x0= PDIV=[13:8]=RW=APLL P=Divide Value=0x3= RSVD=[7:3]=–=Reserved=0x0= SDIV=[2:0]=RW=APLL S=Divide Value=0x1= = 5.9.1.21 APLL_CON0_L5... 
    Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-64  
5.9.1.20 APLL_CON0_L6 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x1108, Reset Value = 0x00C8_0301 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
FSEL=[27]=RW=APLL FSEL value=0x0=
RSVD=[26]=–=Reserved=0x0=
MDIV=[25:16]=RW=APLL M=Divide Value=0xC8=
RSVD=[15:14]=–=Reserved=0x0=
PDIV=[13:8]=RW=APLL P=Divide Value=0x3=
RSVD=[7:3]=–=Reserved=0x0=
SDIV=[2:0]=RW=APLL S=Divide Value=0x1=
=
5.9.1.21 APLL_CON0_L5...
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