Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-15  
 
    Figure 5-3   Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 2 CMU_TOP
EPLL(PLL3600)
0
1
DPTX_PHYSCLK_DPTXPHY
SCLKEPLL
MUXEPLL
MUXVPLL
FOUTEPLL
FOUTVPLL
0
1MOUTACLK_300_DISP1_MID
MUXACLK_300_DISP1_MID
ACLK_300_DISP1DIVACLK_300_DISP1(1~8) /1
USB_HOST20_PHYSCLK_UHOSTPHY
DIVACLK_200(1~8) /4
DIVACLK_266(1~8) /3
ACLK_266
G3D_BLK
CMU_ISP
ACLK_ISP
DIVISPDIV0(1~8) /2
ACLK_DIV0
MAU_BLK
MFC_BLK
GEN_BLK (JPGX_DIV)...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-16  
Figure 5-4 and Figure 5-5 illustrate the Exynos 5250 clock generation circuit (special clocks) 
 
    Figure 5-4   Exynos 5250 Clock Generation Circuit (Special Clocks) 1 
 MUXMMC0~3
MOUTMMC0~3
FSYS_BLK
SCLK_MMC0~3DIVMMC0~3(1~16)DIVMMC0~3_PRE(1~256)
XXTI
SCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHY
SCLKVPLLSCLKCPLL
GEN_BLK
SCLKMPLL_USER
SCLKCPLL
0
1DIVUSBDRD30(1~16)
SCLK_USBRD30
MOUTUSBDRD30
ISP_BLK
DIVPWM_ISP(1~16)
SCLK_PWM_ISP...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-17  
 
    Figure 5-5   Exynos 5250 Clock Generation Circuit (Special Clocks) 2 
Caution: In Figure 5-2 and Figure 5-5, muxes with grey color are glitch-free. For glitch-free clock muxes, 
ensure that all clock sources are running when clock selection is changed. 
For clock dividers, ensure that input clock is running when divider value is changed DIVAUDIO0(1~16)
SCLK_AUDIO0
MUXAUDIO0
DIVAUDIO1(1~16)
SCLK_AUDIO1
MUXAUDIO1
DIVAUDIO2(1~16)...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-18  
Table 5-5 through Table 5-10 show maximum input frequency for each clock divider. 
Dividers in CMU_CPU block need overdrive to divide 1700 MHz or 340 MHz (DIV_PCLK_DBG) input clocks. 
Table 5-5   Maximum Input Frequency for Clock Divider-1 
Block Divider MAX Input Frequency (MHz) 
CMU_TOP 
DIV_CLKOUT 1000 
DIV_ACLK_166 1000 
DIV_ACLK_200 800 
DIV_ACLK_266 800 
DIV_ACLK_300_DISP1 800 
DIV_ACLK_300_GSCL 800 
DIV_ACLK_333 1000...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-19  
Table 5-6   Maximum Input Frequency for Clock Divider-2 
Block Divider MAX Input Frequency (MHz) 
CMU_TOP 
DIV_CAM_BAYER 800 
DIV_DP1_EXT_MST_VID 900 
DIV_FIMD1 900 
DIV_GSCL_WRAP_A 800 
DIV_GSCL_WRAP_B 800 
DIV_HDMI_PIXEL 900 
DIV_I2S1 100 
DIV_I2S2 100 
DIV_JPEG 333 
DIV_MIPI1 920 
DIV_MIPI1_PRE 115 
DIV_MMC0 800 
DIV_MMC0_PRE 800 
DIV_MMC1 800 
DIV_MMC1_PRE 800 
DIV_MMC2 800 
DIV_MMC2_PRE 800 
DIV_MMC3 800 
DIV_MMC3_PRE 800 
DIV_PCM0...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-20  
Table 5-7   Maximum Input Frequency for Clock Divider-3 
Block Divider MAX Input Frequency (MHz) 
CMU_TOP 
DIV_PCM2 100 
DIV_PWM 800 
DIV_PWM_ISP 800 
DIV_SATA 800 
DIV_SPI0 800 
DIV_SPI0_ISP 800 
DIV_SPI0_ISP_PRE 100 
DIV_SPI0_PRE 100 
DIV_SPI1 800 
DIV_SPI1_ISP 800 
DIV_SPI1_ISP_PRE 100 
DIV_SPI1_PRE 100 
DIV_SPI2 800 
DIV_SPI2_PRE 100 
DIV_UART0 800 
DIV_UART1 800 
DIV_UART2 800 
DIV_UART3 800 
DIV_UART_ISP 800 
DIV_USBDRD30 800 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-21  
Table 5-8   Maximum Input Frequency for Clock Divider-4 
Block Divider MAX Input Frequency (MHz) 
CMU_CPU 
DIV_CLKOUT 1265 
DIV_ACP (not used) 1700 
DIV_APLL 1700 
DIV_ARM 1700 
DIV_ARM2 1700 
DIV_ATB 1700 
DIV_COPY 800 
DIV_CPUD 1700 
DIV_HPM 800 
DIV_PCLK_DBG 340 
DIV_PERIPH (not used) 1700 
CMU_ISP 
DIV_CLKOUT 550 
DIV_ISPDIV0 266 
DIV_ISPDIV1 266 
DIV_MPWMDIV 66 
DIV_MCUISPDIV0 400 
DIV_MCUISPDIV1 400 
CMU_LEX 
DIV_CLKOUT 266...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-22  
Table 5-9   Maximum Input Frequency for Clock Divider-5 
Block Divider MAX Input Frequency (MHz) 
CMU_R0X DIV_CLKOUT 266 
DIV_PR0X 266 
CMU_R1X DIV_CLKOUT 266 
DIV_PR1X 266 
CMU_ACP 
DIV_CLKOUT 500 
DIV_ACLK_ACP 800 
DIV_PCLK_ACP 266 
DIV_ACLK_SYSLFT 800 
DIV_PCLK_SYSLFT 400 
DIV_EFPHY_SYSLFT 800 
CMU_CDREX 
DIV_CLKOUT 900 
DIV_MCLK_CDREX 800 
DIV_PCLK_CDREX 266 
DIV_MCLK_CDREX2 800 
DIV_ACLK_CDREX 800 
DIV_ACLK_SFRTZASCP 400...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-23  
5.5 Clock Configuration Procedure 
 You should follow these rules while changing clock configuration: You should run all inputs of a glitch-free 
mux. 
 You should not select the output of PLL when a PLL is turned off. 
Basic SFR Configuration Flows: 
1. Change the system clock divider values as: 
 CLK_DIV_CPU0[31:0]    = target value 0; 
 CLK_DIV_CORE0[31:0]   = target value 1; 
 CLK_DIV_CDREX[31:0]   = target value 2; 
...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-24  
5. Turn on a PLL 
 (A, M, B, C, E, G, V) PLL_CON0[31] = 1; 
     // Turn on a PLL (Refer to (A, M, B, C, E, G, V) PLL_CON0 SFRs 
for more information) 
 wait_lock_time;  
     // Wait until the PLL is locked 
 MUX_(A, M, B, C, E, G, V) PLL_SEL = 1; 
     // After PLL output clock is stabilized, select the PLL output  
     clock instead of input reference clock. (Refer to CLK_SRC_CPU 
     SFR for APLL, CLK_SRC_CORE1 SFR for MPLL,...