Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-307  
4.4.1.446 EXT_INT50CON 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0700, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
RSVD=[27]=–=Reserved=0x0=
EXT_INT50=
_CON[6]=[26:24]=RW=
Setting the signaling method=of EXT_INT50[6]=
0x0 = Sets Low level=
0x1 = Sets High level=
0x2 = Triggers Falling edge =
0x3 = Triggers Rising edge==
0x4 = Triggers Both edge==
0x5 to 0x7 = Reserved=
0x0=...

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-308  
Name Bit Type Description Reset Value 
EXT_INT50 
_CON[1] [6:4] RW 
Setting the signaling method of EXT_INT50[1] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge  
0x3 = Triggers Rising edge  
0x4 = Triggers Both edge  
0x5 to 0x7 = Reserved 
0x0 
RSVD [3] – Reserved 0x0 
EXT_INT50 
_CON[0] [2:0] RW 
Setting the signaling method of EXT_INT50[0] 
0x0 = Sets Low level 
0x1 = Sets High level 
0x2 = Triggers Falling edge...

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-309  
4.4.1.447 EXT_INT50_FLTCON0 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0800, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
FLTEN1[3] [31] RW 
Enables Filter for EXT_INT50[3] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[3] [30:24] RW Filtering width of EXT_INT50[3] 0x00 
FLTEN1[2] [23] RW 
Enables Filter for EXT_INT50[2] 
0x0 = Disables 
0x1 = Enables 
0x0 
FLTWIDTH1[2] [22:16] RW Filtering width of...

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-310  
4.4.1.449 EXT_INT50_MASK 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0900, Reset Value = 0x0000_007F 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0000000=
EXT_INT50=
_MASK[6]=[6]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[5]=[5]=RW=0x0 = Enables Interrupt=
0x1 = Masks Interrupt=0x1=
EXT_INT50=
_MASK[4]=[4]=RW=0x0 = Enables Interrupt=
0x1 ==Masks Interrupt=0x1=
EXT_INT50=...

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-311  
4.4.1.451 EXT_INT_GRPPRI_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B00, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x00000000=
EXT_INT=
_GRPPRf=[0]=RW=
EXT_INT groups priority rotate enable=
0x0===Does not=rotate (Fixed),=
0x1===Enables rotate=
0x0=
=
4.4.1.452 EXT_INT_PRIORITY_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B04, Reset Value = 0x0000_0000 
Name...

Samsung Confidential  
Exynos 5250_UM 4 Pad Control 
 4-312  
4.4.1.454 EXT_INT_SERVICE_PEND_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B0C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] RW Reserved 0x0000000 
SVC_PEND [7:0] RW 0x0 = Does not occur 
0x1 = Interrupt occurs 0x00 
 
4.4.1.455 EXT_INT_GRPFIXPRI_XD 
 Base Address: 0x0386_0000 
 Address = Base Address + 0x0B10, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:5]...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-1  
5 Clock Controller 
This chapter describes the Clock Management Units (CMUs) of Exynos 5250. These CMUs control Phase Locked 
Loops (PLLs) and generate system clocks for CPU, buses, and function clocks for individual IPs in Exynos 5250. 
They also communicate with Power Management Unit (PMU) to stop clocks before entering certain low power 
mode. It results in reducing power consumption by minimizing clock toggling. 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-2  
5.1 Clock Domains 
In Exynos 5250, function blocks are clocked asynchronously with each other. Therefore they provide more 
freedom in choosing operating frequencies and make physical implementation easier. 
 CPU block contains ARM A15 Dual-core processor (E4D), L2 cache controller, and CoreSight. E4D Dual-core 
operates at 1.7 GHz and CoreSight at 200 MHz. CMU in CPU block (CMU_CPU) generates all the necessary 
clocks for IPs in CPU...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-3  
Typical operating frequencies for each function block are described in Table 5-1. 
Table 5-1   Operating Frequencies in Exynos 5250 
Function Block Description Typical Operating Frequency 
CPU E4D Dual-core 1.7 GHz 
CoreSight 200 MHz 
DMC DREXII 400 MHz/533 MHz/800 MHz 
SSS, MIU 266 MHz/400 MHz 
LEX Data Bus/Peripheral Bus 266 MHz/133 MHz 
R0X/R1X Data Bus/Peripheral Bus 266 MHz/133 MHz 
G3D 3D Graphics Engine 533 MHz 
MFC Multi-format...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-4  
5.2 Clock Declaration 
The top-level clocks in Exynos 5250 are: 
 Clocks from clock pads, that is, XRTCXTI and XXTI. 
 Clocks from CMUs (for example, ARMCLK, ACLK, HCLK, and SCLK) 
ARMCLK specifies clock for E4D Dual-core. 
SCLK (special clock) specifies all the clocks except bus clocks and processor core clock. 
 Clocks from USB PHY 
 Clocks from GPIO pads 
 
5.2.1 Clocks from Clock Pads 
Clock pads provide these clocks.  
 XRTCXTI:...