Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-5  
5.2.2 Clocks from CMU 
CMUs generate internal clocks with intermediate frequencies using clocks from the clock pads (i.e., XRTCXTI and 
XXTI), seven PLLs (i.e., APLL, MPLL, BPLL, CPLL, EPLL, GPLL and VPLL) and USB PHY and HDMI PHY 
clocks. Some of these clocks can be selected, pre-scaled, and provided to the corresponding modules.  
It is recommended to use 24 MHz input clock source for APLL, MPLL, BPLL, CPLL, EPLL, GPLL and VPLL. 
In...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-6  
5.3 Clock Relationship 
Clocks have these relationships: 
 CPU_BLK clocks 
 freq. (ARMCLK) = freq. (MOUTCPU)/n, where n = 1 to 64 
 freq. (ACLK_CPUD) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (ACLK_ACP) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (PERIPHCLK) = freq. (ARMCLK)/n, where n = 1 to 8 
 freq. (ATCLK) = freq. (MOUTCPU)/n, where n = 1 to 8 
 freq. (PCLK_DBG) = freq. (ATCLK)/n, where n = 1 to 8 
 
 DMC_BLK clocks 
 freq....

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-7  
 CMU_TOP clocks  
 freq. (ACLK_400_G3D) = freq. (MOUTACLK_400_G3D)/n, where n = 1 to 8  
 freq. (ACLK_400_IOP) = freq. (MOUTACLK_400_IOP)/n, where n = 1 to 8  
 freq. (ACLK_400_ISP) = freq. (MOUTACLK_400_ISP)/n, where n = 1 to 8 
 freq. (ACLK_333) = freq. (MOUTACLK_333)/n, where n = 1 to 8  
 freq. (ACLK_300_DISP1) = freq. (MOUTACLK_300_DISP1)/n, where n = 1 to 8  
 freq. (ACLK_300_GSCL) = freq. (MOUTACLK_300_GSCL)/n, where n = 1 to...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-8  
Values for high-performance operation: 
 freq. (ARMCLK) = 1.7 GHz 
 freq. (ACLK_CPUD) = 450 MHz, 500 MHz 
 freq. (PERIPHCLK) = 169 MHz, 125 MHz 
 freq. (ATCLK) = 200 MHz 
 freq. (PCLK_DBG) = 100 MHz 
 freq. (MCLK_CDREX) = 800 MHz, 667 MHz, 533 MHz, 400 MHz 
 freq. (ACLK_CDREX) = 400 MHz, 333 MHz, 266 MHz, 200 MHz 
 freq. (PCLK_CDREX) = 133 MHz 
 freq. (ACLK_ACP) = 266 MHz 
 freq. (PCLK_ACP) = 133 MHz 
 freq. (ACLK_DLEX) = 266 MHz...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-9  
 PLL 
 APLL primarily drives CPU_BLK clocks. It can generate up to 1.7 GHz.  
 MPLL primarily drives DMC_BLK, LEX_BLK, R0X_BLK, R1X_BLK and TOP block clocks. It can generate 
up to 1.6 GHz. MPLL can also generate CPU_BLK clocks when APLL is blocked for locking during 
Dynamic Voltage Frequency Scaling (DVFS).  
 BPLL is primarily used to generate 1066 MHz, providing 533 MHz to DMC_BLK. 
 CPLL is primarily used to generate 333 MHz,...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-10  
5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL 
Table 5-2 lists the APLL, MPLL, BPLL, CPLL and GPLL PMS value. 
Table 5-2   APLL, MPLL, BPLL, CPLL and GPLL PMS Value 
FIN 
(MHz) 
Target FOUT 
(MHz) P M S AFC_ENB AFC FVCO 
(MHz) 
FOUT 
(MHz) 
24 200 3 100 2 0 0 800 200 
24 333 4 222 2 0 0 1332 333 
24 400 3 100 1 0 0 800 400 
24 533 12 533 1 0 0 1066 533 
24 600 4 200 1 0 0 1200 600 
24 667 7 389 1 0 0 1333.71429...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-11  
5.3.2 Recommended PLL PMS Value for EPLL 
Table 5-3 lists the EPLL PMS value. 
Table 5-3   EPLL PMS Value 
FIN (MHz) Target FOUT 
(MHz) P M S K FOUT (MHz) 
24 48.0000 2 64 4 0 48 
24 96.0000 2 64 3 0 96 
24 144.0000 2 96 3 0 114 
24 192.0000 2 64 2 0 192 
24 288.0000 2 96 2 0 288 
24 84.0000 2 112 4 0 84 
24 50.0000 2 67 4 43691 (  21845) 50 
24 80.0000 2 107 4 43691 (  21845) 80 
24 32.7680 3 131 5 4719 32.768 
24 49.1520 3 98 4 19923...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-12  
5.3.3 Recommended PLL PMS Value for VPLL 
Table 5-4 describes the VPLL PMS value. 
Table 5-4   VPLL PMS Value 
FIN 
(MHz) 
Target FOUT 
(MHz) P M S K MFR MRR SSCG_EN 
24 
54 2 72 4 0   0 
108 2 72 3 0   0 
74.25 2 99 4 0   0 
148.5 2 99 3 0   0 
222.75 2 74 2 16384   0 
371.25 2 62 1 57344 (  8192)   0 
445.5 2 74 1 16384   0 
74.176 2 99 4 59070 (  6466)   0 
148.352 2 99 3 59070 (  6466)   0 
222.528 3 111 2 17302 ...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-13  
5.4 Clock Generation 
Figure 5-2 through Figure 5-5 illustrate block diagram of the clock generation logic. An external crystal clock is 
connected to the oscillation amplifier. The PLL converts low input frequency to high-frequency clock that Exynos 
5250 requires. The clock generator block also includes a built-in logic to stabilize the clock frequency after each 
system reset, because clock takes time for stabilizing. 
Figure 5-2...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-14  
Figure 5-2 and Figure 5-3 illustrate the Exynos 5250 clock generation circuit. (CPU, BUS, DRAM Clocks) 
 
    Figure 5-2   Exynos 5250 Clock Generation Circuit (CPU, BUS, DRAM Clocks) 1 CMU_CDREX
CMU_CORE
MUXMPLL
MOUTMPLL
0
1
DIVRSVD3_CORE(1~16)
MUXPWI
MOUTPWI
XXTIXusbXTISCLK_HDMI27MSCLK_DPTXPHYSCLK_UHOSTPHYSCLK_HDMIPHYSCLKMPLLSCLKEPLLSCLKVPLL
SCLKMPLL
FOUTMPLL
DIVRSVD1_CORE(1~128)
DIVRSVD2_CORE(1~128)
DIVCORED(1~8)
DIVCOREP(1~8)...