Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-25  
5.5.1 Clock Gating 
Exynos 5250 can disable the clock operation of each IP if it is not required. Disabling the clock operation reduces 
the dynamic power. 
There are two types of clock gating control registers to Disable/Enable clock operation: 
 Clock gating control register for function block 
 Clock gating control register for IP 
These two registers are AND operated together to generate a final clock gating enable signal. As a...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-26  
5.6 Special Clock Description 
Special Clock Description section describes special clocks in Exynos 5250. 
 
5.6.1 Special Clock Table 
Table 5-11 describes the special clocks in Exynos 5250. 
Table 5-11   Special Clocks in Exynos 5250 
Name Description Range Source 
SCLK_CAM0, 1 Reference clock for external 
CAM device CAM spec All possible clock sources 
SCLK_CAM_BAYER Reference clock for external 
CAM device CAM spec All possible clock...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-27  
 All possible clock sources are:  
 XXTI  
 SCLK_HDMI24M  
 SCLK_DPTXPHY  
 SCLK_UHOSTPHY  
 SCLK_HDMIPHY  
 SCLKMPLL_USER  
 SCLKCPLL  
 SCLKEPLL  
 SCLKGPLL 
 SCLKVPLL 
 XXTI refers to external crystal 
 SCLK_DPTXPHY refers to DPTX PHY output clock 
 SCLK_UHOSTPHY refers to USB PHY 48 MHz output clock 
 SCLK_HDMI24M refers to HDMI PHY output clock 
 SCLK_HDMIPHY refers to HDMI PHY (PIXEL_CLK) output clock 
...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-28  
5.7 CLKOUT 
You can monitor certain clocks in Exynos 5250 using XCLKOUT port. Each of the nine CMUs in Exynos 5250 
contains CLKOUT control logic where one of the clocks in that CMU is selected and divided if necessary. The 
generated CLKOUT signal from each CMU is fed to power management unit and multiplexed with other CLKOUT 
signals and XXTI, RTC_TICK_SRC, and RTCCLK clocks. Figure 5-4 illustrates CLKOUT control logic in Exynos 
5250....

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-29  
Table 5-13 lists the CLKOUT input clock selection information. 
Table 5-13   CLKOUT Input Clock Selection Information (Part 1) 
NO CMU_CPU CMU_CORE CMU_CDREX CMU_ISP CMU_TOP PMU 
0 APLL_FOUT MPLL_FOUT 
_RGT MCLK_CDREX ACLK_266 EPLL_FOUT PMU_DEBUG 
1 – – ACLK_CDREX ACLK_DIV0 VPLL_FOUT CMU_CDREX 
2 – – PCLK_CDREX ACLK_DIV1 CPLL_FOUT CMU_CORE 
3 – – RCLK_CDREX SCLK_MPW M 
_ISP SCLK_HDMI24M CMU_ISP 
4 ARMCLK – – – SCLK_DPTXPHY CMU_LEX 
5...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-30  
Table 5-14 lists the CLKOUT input clock selection information (Part 2). 
Table 5-14   CLKOUT Input Clock Selection Information (Part 2) 
NO CMU_LEX CMU_R0X CMU_R1X CMU_ACP 
0 ACLK_266 ACLK_266 ACLK_266 SCLK_MPLL_LFT 
1 ACLK_DLEX ACLK_DR0X ACLK_DR1X ACLK_ACP 
2 ACLK_PLEX ACLK_PR0X ACLK_PR1X PCLK_ACP 
3 – – – ACLK_SYSLFT 
4 – – – PCLK_SYSLFT 
5 – – – EFCLK_SYSLFT 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-31  
5.8 I/O Description 
Signal I/O Description Pad Type 
XXTI Input External oscillator pad XXTI Dedicated 
EPLLFILTER Input/Output Pad for EPLL loop Filter capacitor XEPLLFILTER Dedicated 
VPLLFILTER Input/Output Pad for VPLL loop Filter capacitor XVPLLFILTER Dedicated 
XCLKOUT Output Clock Out pad XCLKOUT Dedicated 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-32  
5.9 Register Description 
Clock controller controls PLLs and clock generation units. This section describes how to control these parts using 
Special Functional Registers (SFRs) in the clock controller. Do not change any reserved area. Changing value of 
reserved area may lead to unexpected behavior. 
Figure 5-5 illustrates the address map of Exynos 5250 clock controller. There are nine CMUs in Exynos 5250 and 
each CMU uses 16 KB address...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-33  
In Figure 5-7, XXX means function block name that is LEX, R0X/R1X, TOP, GSCL, MFC, G3D, GEN, DISP1, 
MAU, FSYS, PERIC, and PERIS.  
Figure 5-7 illustrates the Exynos 5250 clock controller address map. 
 
    Figure 5-7   Exynos 5250 Clock Controller Address Map 
 
 0x1001_4000
0x1002_4000
CMU_ACP
CMU_ISP
CMU_TOP
CMU_LEX
0x1001_8000
0x1001_C000
0x1002_0000
0x1002_8000
0x000
Reserved
CLK_DIV_XXX
CLK_DIV_STAT_XXX
CLK_GATE_IP_XXX...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-34  
5.9.1 Register Map Summary 
 Base Address: 0x1001_0000 
Register Offset Description Reset Value 
APLL_LOCK 0x0000 Control PLL Locking period for APLL 0x0000_0FFF 
RSVD 0x0004 
to 0x00FC Reserved Undefined 
APLL_CON0 0x0100 Control PLL output frequency for APLL 0x00C8_0601 
APLL_CON1 0x0104 Control PLL AFC 0x0020_3800 
RSVD 0x0108 
to 0x01FC Reserved Undefined 
CLK_SRC_CPU 0x0200 Select Clock Source for CMU_CPU 0x0000_0000 
RSVD 0x0204 
to...