Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-35  
Register Offset Description Reset Value 
PWR_CTRL2 0x1024 Power Control register 0x0000_0000 
RSVD 0x1028 
to 0x10FC Reserved Undefined 
APLL_CON0_L8 0x1100 APLL Control (performance level-8) 0x00C8_0301 
APLL_CON0_L7 0x1104 APLL Control (performance level-7) 0x00C8_0301 
APLL_CON0_L6 0x1108 APLL Control (performance level-6) 0x00C8_0301 
APLL_CON0_L5 0x110C APLL Control (performance level-5) 0x00C8_0301 
APLL_CON0_L4 0x1110 APLL Control...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-36  
Register Offset Description Reset Value 
CLK_DIV_CORE1 0x4504 Set Clock Divider ratio for CMU_CORE (part2) 0x0000_0000 
CLK_DIV_SYSRGT 0x4508 Set Clock Divider ratio for CMU_CORE (part3 : 
SYSMEM_RGT) 0x0000_0000 
RSVD 0x450C 
to 0x45FC Reserved Undefined 
CLK_DIV_STAT_CORE0 0x4600 Clock Divider Status for CMU_CORE (part1) 0x0000_0000 
CLK_DIV_STAT_CORE1 0x4604 Clock Divider Status for CMU_CORE (part2) 0x0000_0000 
CLK_DIV_STAT_SYSRG
T...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-37  
Register Offset Description Reset Value 
CLK_GATE_BUS_SYSLF
T 0x8920 Clock gating of clock for SYSLFT_BLK 0xFFFF_FFFF 
RSVD 0x8924 
to 0x892C Reserved Undefined 
RSVD 0x8934 
to 0x89FC Reserved Undefined 
CLKOUT_CMU_ACP 0x8A00 CLKOUT Control register 0x0001_0000 
CLKOUT_CMU_ACP 
_DIV_STAT 0x8A04 Clock Divider Status for CLKOUT  0x0000_0000 
RSVD 0x8A08 
to 0x8A0C Reserved Undefined 
UFMC_CONFIG 0x8A10 UFMC Configuration 0x0000_0000 
RSVD...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-38  
 Base Address: 0x1002_0000 
Register Offset Description Reset Value 
RSVD 0x0000 
to 0x001C Reserved Undefined 
CPLL_LOCK 0x0020 Control PLL Locking period for CPLL 0x0000_0FFF 
RSVD 0x0024 
to 0x002C Reserved Undefined 
EPLL_LOCK 0x0030 Control PLL Locking period for EPLL 0x0000_0FFF 
RSVD 0x0034 
to 0x003C Reserved Undefined 
VPLL_LOCK 0x0040 Control PLL Locking period for VPLL 0x0000_0FFF 
RSVD 0x0044 
to 0x004C Reserved Undefined...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-39  
Register Offset Description Reset Value 
RSVD 0x0230 
to 0x023C Reserved Undefined 
CLK_SRC_MAU 0x0240 Select Clock Source for MAUDIO_BLK 0x0000_0001 
CLK_SRC_FSYS 0x0244 Select Clock Source for FSYS_BLK 0x0000_0000 
CLK_SRC_GEN 0x0248 Select Clock Source for GEN_BLK 0x0000_0000 
RSVD 0x024C Reserved Undefined 
CLK_SRC_PERIC0 0x0250 Select Clock Source for connectivity IPs (part1) 0x0000_0000 
CLK_SRC_PERIC1 0x0254 Select clock source for...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-40  
Register Offset Description Reset Value 
CLK_MUX_STAT_TOP2 0x0418 Clock MUX Status for CM_TOP (part3) 0x0111_1100 
CLK_MUX_STAT_TOP3 0x041C Clock MUX Status for CM_TOP (part4) 0x0111_1111 
RSVD 0x0420 
to 0x050C Reserved Undefined 
CLK_DIV_TOP0 0x0510 Set Clock Divider ratio for CMU_TOP (part1) 0x0000_0000 
CLK_DIV_TOP1 0x0514 Set Clock Divider ratio for CMU_TOP (part2) 0x0000_0000 
RSVD 0x0518 
to 0x051C Reserved Undefined 
CLK_DIV_GSCL...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-41  
Register Offset Description Reset Value 
RSVD 0x05A4 
to 0x060C Reserved Undefined 
CLK_DIV_STAT_TOP0 0x0610 Clock Divider Status for CMU_TOP (part1) 0x0000_0000 
CLK_DIV_STAT_TOP1 0x0614 Clock Divider Status for CMU_TOP (part2) 0x0000_0000 
RSVD 0x0618 
to 0x061C Reserved Undefined 
CLK_DIV_STAT_GSCL 0x0620 Clock Divider Status for GSCL_BLK 0x0000_0000 
RSVD 0x0624 
to 0x0628 Reserved Undefined 
CLK_DIV_STAT_DISP1_0 0x062C Clock Divider...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-42  
Register Offset Description Reset Value 
CLK_GATE_TOP 
_SCLK_DISP1 0x0828 Gating Special Clock for DISP1_BLK 0xFFFF_FFFF 
CLK_GATE_TOP 
_SCLK_GEN 0x082C Gating Special Clock for GEN_BLK 0xFFFF_FFFF 
RSVD 0x0830 
to 0x0838 Reserved Undefined 
CLK_GATE_TOP 
_SCLK_MAU 0x083C Gating Special Clock for MAUDIO_BLK 0xFFFF_FFFF 
CLK_GATE_TOP 
_SCLK_FSYS 0x0840 Gating Special Clock for FSYS_BLK 0xFFFF_FFFF 
RSVD 0x0844 
to 0x084C Reserved Undefined...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-43  
Register Offset Description Reset Value 
RSVD 0x09A4 
to 0x09FC Reserved Undefined 
CLKOUT_CMU_TOP 0x0A00 CLKOUT Control Register 0x0001_0000 
CLKOUT_CMU_TOP 
_DIV_STAT 0x0A04 Clock Divider Status for CLKOUT  0x0000_0000 
RSVD 0x0A08 
to 0x41FC Reserved Undefined 
CLK_SRC_LEX 0x4200 Select Clock Source for CMU_LEX 0x0000_0000 
RSVD 0x4204 
to 0x43FC Reserved Undefined 
CLK_MUX_STAT_LEX 0x4400 Clock MUX Status for CMU_LEX 0x0000_0001 
RSVD...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-44  
Register Offset Description Reset Value 
CLK_DIV_R1X 0xC500 Set clock Divider ratio for CMU_R1X 0x0000_0000 
RSVD 0xC504 
to 0xC5FC Reserved Undefined 
CLK_DIV_STAT_R1X 0xC600 Clock Divider Status for CMU_R1X 0x0000_0000 
RSVD 0xC604 
to 0xC7FC Reserved Undefined 
CLK_GATE_IP_R1X 0xC800 Control IP Clock Gating for R1X_BLK 0xFFFF_FFFF 
RSVD 0xC804 
to 0xC9FC Reserved Undefined 
CLKOUT_CMU_R1X 0xCA00 CLKOUT control register 0x0001_0000...