Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-45  
 Base Address: 0x1003_0000 
Register Offset Description Reset Value 
RSVD 0x0000 
to 0x000C Reserved Undefined 
BPLL_LOCK 0x0010 Control PLL Locking period of BPLL 0x0000_0FFF 
RSVD 0x0014 
to 0x010C Reserved Undefined 
BPLL_CON0 0x0110 Control PLL output frequency for BPLL 0x00C8_0601 
BPLL_CON1 0x0114 Control PLL AFC 0x0020_3800 
RSVD 0x0118 
to 0x01FC Reserved Undefined 
CLK_SRC_CDREX 0x0200 Select Clock Source for CMU_CDREX...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-46  
Register Offset Description Reset Value 
LPDDR3PHY_CTRL 0x0A10 Reset for LPDDR3HPHY. This reset is used for 
DDR3 memory 0x0000_0001 
RSVD 0x0A14 
to 0x0A1C Reserved Undefined 
LPDDR3PHY_CON3 0x0A20 DREX ADDR pin Change 0x0000_0000 
PLL_DIV2_SEL 0x0A24 Selection for PLL_FOUT 0x0000_0000 
RSVD 0x0A28 
to 0xFFFC Reserved Undefined 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-47  
SFRs consist of nine parts.  
 The SFRs with address 0x1001_0000 to 0x1001_3FFF control clock-related logics for CPU block. They 
control APLL, Clock Source Selection, and Clock Divider Ratio for CPU-related logics. 
 The SFRs with address 0x1001_4000 to 0x1001_7FFF control clock-related logics for DMC block (part 1).  
They control MPLL, Clock Source Selection, Clock Divider Ratio, and Clock Gating for DMC peripheral sub-
block. 
 The...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-48  
5.9.1.1 APLL_LOCK 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0FFF 
Name Bit Type Description Reset Value 
RSVD [31:20] –=Reserved=0x0=
PLL_LOCKTIME=[19:0]=RW=
Required=period(in=cycles)=to generate a stable=
clock output=
The maximum lock time can be up to 250= PDIV 
cycles of PLLs FIN (XXTI). 
0xF_FFFF 
 
  

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-49  
5.9.1.2 APLL_CON0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0100, Reset Value = 0x00C8_0601 
Name Bit Type Description Reset Value 
ENABLE [31] RW 
PLL Enable control 
0 = Disables PLL 
1 = Enables PLL 
0x0 
RSVD [30] –=Reserved=0x0=
LOCKED=[29]=o=
PLL Locking indication=
0 = Unlocks PLi=
1 = Locks PLi=
0x0=
RSVD=x28]=–=Reserved=0x0=
FSEL=[27]=RW=
Monitoring=Frequency Select pin=
0 = FVCO_OUT== FREF=
1 = FVCO_OUT = FVCl=...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-50  
Do not set the value of PDIV[5:0] or MDIV[9:0] to all zeros. 
Refer to 5.3.1 Recommended PLL PMS Value for APLL, MPLL, BPLL, CPLL and GPLL for more information on 
recommended PMS values. 
SDIV[2:0] controls division ratio of Scaler as described in Table 5-15. 
Table 5-15 lists the Division Ratio of Scaler. 
Table 5-15   Division Ratio of Scaler 
S[2:0] Division Ratio 
000  2^0 = 1 
001 2^1 = 2 
010 2^2 = 4 
011 2^3 = 8 
100 2^4 = 16 
101...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-51  
5.9.1.3 APLL_CON1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0104, Reset Value = 0x0020_3800 
Name Bit Type Description Reset Value 
RSVD [31:22] –=Reserved=0x0=
DCC_ENB=[21]=RW=
Enables Duty Cycle Corrector (DCC)=
(only for monitoring)=
0 = Enables DCC=
1 = Disables DCC=
0x1=
AFC_ENB=x20]=RW=
Decides=whether AFC is enabled or not (Active-=
low)=
0 = Enables AFC=
1 = Disables AFC=
0x0=
RSVD=x19:17]=–=Reserved=0x0=...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-52  
5.9.1.4 CLK_SRC_CPU 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0200, Reset Value = 0x0000_0000; 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
MUX_HPM_SEi=[20]=RW=
Control MUu_HPM=
0 = MOUT_APLi=
1 = SCLK_MPLi=
0x0=
RSVD=[19:17]=–=Reserved=0x0=
MUX_CPr_SEL=[16]=RW=
Control MUu_CPU=
0 = MOUT_APLi=
1 = SCLK_MPLi=
0x0=
RSVD=[15:1]=–=Reserved=0x0=
MUX_APLL_SEL=[0]=RW=
Control MUu_APLL=
0 = XXTI=
1 =...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-53  
5.9.1.6 CLK_DIV_CPU0 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0500, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ARM2_RATIO=[30:28]=RW=DIV_ARM2=clock divider Ratio=
ARMCLK== DOUT_ARM/(ARM2_RATIO + 1)=0x0=
RSVD=[27]=–=Reserved=0x0=
APLL_RATIO=[26:24]=RW=DIV_APLL clock divider Ratio=
SCLK_APLi== MOUT_APLL/(APLL_RATIO + 1)=0x0=
RSVD=[23]=–=Reserved=0x0=
PCLK_DBG=...

Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-54  
5.9.1.7 CLK_DIV_CPU1 
 Base Address: 0x1001_0000 
 Address = Base Address + 0x0504, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:7] –=Reserved=0x0=
HPM_RATIl=[6:4]=RW=DIV_HPM clock divider Ratio=
SCLK_HPM = DOUT_COPY/(HPM_RATIO + 1)=0x0=
RSVD=[3]=–=Reserved=0x0=
COPY_RATIO=[2:0]=RWu=DIV_COPY clock divider Ratio=
DOUT_COPY = MOUT_HPM/(COPY_RATIO + 1)=0x0=
=
=