Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-8  
13.3.8 Flowcharts of Operations in Each Mode 
Execute these steps before any I2C Tx/Rx operations: 
1. When required, write own slave address on I2CADD register 
2. Set I2CCON register: 
 a)  Enable interrupt 
 b)  Define SCL period 
3. Set I2CSTAT to enable Serial Output 
Figure 13-6 illustrates operations in Master/Transmitter mode. 
 
    Figure 13-6   Operations in Master/Transmitter Mode W rite slave address to
I2CDS.
W rite 0xF0...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-9  
NOTE: When Master transmit mode, stop sequence of I2C_HDMI and I2C_SATAPHY is as follows  
Write 0xD0 to I2CSTAT  clear pending bit  Wait until the stop condition take effect  
 Write 0xC0 to I2CSTAT  END 
   

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-10  
Figure 13-7 illustrates operations in Master/Receiver mode. 
 
    Figure 13-7   Operations in Master/Receiver Mode 
NOTE: When Master receiver mode, stop sequence of I2C_HDMI and I2C_SATAPHY is as follows  
Write 0x90 to I2CSTAT  clear pending bit  Wait until the stop condition take effect  
 Write 0x80 to I2CSTAT  END 
 
 Write slave address to
I2CDS.
Write 0xB0 (M/R Start)
to I2CSTAT.
The data of the I2CDS
(Slave address) is...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-11  
Figure 13-8 illustrates operations in Slave/Transmitter mode. 
 
    Figure 13-8   Operations in Slave/Transmitter Mode 
 I2C detects start signal. and, I2CDS
receives data.
I2C compares I2CADD and I2CDS
(the received slave address).
W rite data to I2CDS.
Clear pending bit to
resume.
The data of the I2CDS
is shifted to SDA.
START
Slave Tx mode has
been configured.
END
Matched?
N
Y
Stop?
Interrupt is pending.
N
Y
 
The I2C address match...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-12  
Figure 13-9 illustrates operations in Slave/Receiver mode. 
 
    Figure 13-9   Operations in Slave/Receiver Mode 
 I2C detects start signal. and, 12CDS
receives data.
I2C compares I2CADD and I2CDS
(the received slave address).
Read data from I2CDS.
Clear pending bit to
resume.
SDA is shifted to I2CDS.
START
Slave Rx mode has
been configured.
END
Matched?
N
Y
Stop?
Interrupt is pending.
N
Y
 
The I2C address match
interrupt is generated.  

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-13  
13.4 I/O Description 
Signal I/O Description Pad Type 
I2C0_SCL Input/Output I2C-bus interface0 Serial Clock Line Xi2c0SCL muxed 
I2C0_SDA Input/Output I2C-bus interface0 Serial Data Line Xi2c0SDA muxed 
I2C1_SCL Input/Output I2C-bus interface1 Serial Clock Line Xi2c1SCL muxed 
I2C1_SDA Input/Output I2C-bus interface1 Serial Data Line Xi2c1SDA muxed 
I2C2_SCL Input/Output I2C-bus interface2 Serial Clock Line XuRTSn_1 muxed 
I2C2_SDA...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-14  
13.5 Register Description 
13.5.1 Register Map Summary 
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address:...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-15  
13.5.1.1 I2CCONn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP)...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-16  
NOTE:  
1 While interfacing with EEPROM, the ACK generation may be disabled before reading the last data to generate the STOP  
  condition in Rx mode. 
2.  An I2C-Bus interrupt occurs when: 
 1) A 1-byte transmit or receive operation is complete. Alternatively, ACK period is finished. 
 2) A general call or a slave address match occurs. 
 3) Bus arbitration fails. 
3. To adjust the setup time of SDA before SCL rising edge, I2CDS should...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-17  
13.5.1.2 I2CSTATn (n = 0 to 7) 
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP)...