Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-18  
Name Bit Type Description Reset Value 
Last-received bit 
status flag [0] R 
I2C-Bus Last-received Bit Status Flag bit 
0 = Last-received bit is 0 (ACK was received) 
1 = Last-received bit is 1 (ACK was not received) 
0 
 
 
  

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-19  
13.5.1.3 I2CADDn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP)...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-20  
13.5.1.4 I2CDSn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP) 
...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-21  
13.5.1.5 I2CLCn (n = 0 to 7)  
 Base Address: 0x12C6_0000 (I2C0) 
 Base Address: 0x12C7_0000 (I2C1) 
 Base Address: 0x12C8_0000 (I2C2) 
 Base Address: 0x12C9_0000 (I2C3) 
 Base Address: 0x12CA_0000 (I2C4) 
 Base Address: 0x12CB_0000 (I2C5) 
 Base Address: 0x12CC_0000 (I2C6) 
 Base Address: 0x12CD_0000 (I2C7) 
 Base Address: 0x12CE_0000 (I2C_HDMI) 
 Base Address: 0x1313_0000 (I2C0_ISP) 
 Base Address: 0x1314_0000 (I2C1_ISP) 
...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-1  
14 Serial Peripheral Interface 
14.1 Overview 
Serial Peripheral Interface (SPI) in Exynos 5250 transfers serial data by using various peripherals. 
SPI includes two 8, 16, 32-bit shift registers to transmit and receive data. It transfers (shifts out serially) and 
receives (shifts in serially) data simultaneously. It supports the protocols for National Semiconductor Microwire 
and Motorola Serial Peripheral Interface.  
 
14.2...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-2  
14.2.1 Operation of Serial Peripheral Interface 
SPI transfers 1-bit serial data between Exynos 5250 and external device. SPI in Exynos 5250 supports CPU or 
DMA to transmit or receive FIFOs separately. It also supports to transfer data in both directions simultaneously. 
SPI has two channels: Tx channel and Rx channel. The Tx channel has the path from Tx FIFO to external device. 
The Rx channel has the path from external...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-3  
14.2.1.4 Packet Number Control 
SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any 
number of packets. SPI stops generating SPICLK when the number of packets is the same as 
PACKET_CNT_REG. The size of one packet depends on channel width.  
NOTE: One packet is 1 byte if channel width is configured as byte, and one packet is 4 bytes if channel width is configured as 
word....

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-4  
14.2.1.7 Feed Back Clock Selection 
Under SPI protocol spec, SPI master should capture the input data launched by slave (MISO) with its internal 
SPICLK.  
When SPI runs at high operating frequency such as 50 MHz, it is difficult to capture the MISO input because the 
required arrival time of MISO, which is an half cycle period in Exynos 5250, is shorter than the arrival time of 
MISO that consists of SPICLK output delay of SPI...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-5  
14.2.1.8 SPI Transfer Format 
Exynos 5250 supports four different formats for data transfer. Figure 14-1 illustrates four waveforms for SPICLK.  
 
    Figure 14-1   SPI Transfer Format  Cycle
MOSI
12345678
MSB654321LSB
654321LSB
SPICLK
MISOMSB
CPOL = 1, CPHA = 1 (Format B)
Cycle
MOSI
12345678
MSB654321LSB
654321LSB*MSB
SPICLK
MISOMSB
CPOL = 1, CPHA = 0 (Format A)
Cycle
MOSI
12345678
654321LSB
654321LSB
SPICLK
MISOLSB*
CPOL =...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-6  
14.3 SPI Input Clock Description 
Figure 14-2 illustrates input clock diagram for SPI. 
 
    Figure 14-2   Input Clock Diagram for SPI 
Exynos 5250 provides SPI with a variety of clocks. As illustrated in the Figure 14-2, SPI uses SCLK_SPI clock, 
which is from clock controller. You can also select SCLK_SPI from various clock sources. Refer to Chapter 7 
Clock Controller to select SCLK_SPI. 
NOTE: SPI has an internal 2x clock...