Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-7  
14.4 I/O Description 
Signal I/O Description Pad Type 
SPI_0_CLK 
SPI_1_CLK 
SPI_2_CLK 
ISP_SPI_0_CLK 
ISP_SPI_1_CLK 
In/Out 
XspiCLK is the serial clock used to control time of 
data transfer. 
 
Out: W hen used as master 
In: W hen used as slave 
XspiCLK_0 
XspiCLK_1 
Xi2s2CDCLK 
XispSPICLK 
XispI2C1SDA 
muxed 
SPI_0_nSS 
SPI_1_nSS 
SPI_2_nSS 
ISP_SPI_0_nSS 
ISP_SPI_1_nSS 
In/Out 
Slave selection signal. All data Tx/Rx...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-8  
14.5 Register Description 
14.5.1 Register Map Summary  
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
Register Offset Description Reset Value 
CH_CFGn 0x0000 Specifies SPI configuration 0x0 
MODE_CFGn 0x0008 Specifies FIFO control 0x0 
CS_REGn 0x000C Specifies slave selection control 0x1...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-9  
14.5.1.1 CH_CFGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0000, Reset Value = 0x0 
Name Bit Type Description Reset Value 
HIGH_SPEED_EN [6] RW 
Slave Tx output time control bit 
When this bit is enabled, slave Tx output time is 
reduced as...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-10  
14.5.1.2 MODE_CFGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0008, Reset Value = 0x0 
Name Bit Type Description Reset Value 
CH_W IDTH [30:29] RW 
00 = Byte    
01 = Halfword  
10 = W ord        
11 = Reserved 
0 
TRAILING_CNT [28:19] RW...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-11  
NOTE:  
1. CH_WIDTH is shift-register width.  
2. BUS_WIDTH is SPI FIFO width. The transfer data size should be aligned with BUS_WIDTH. 
 For example, TX/RX data size must be aligned with 4 bytes if BUS_WIDTH is word.  
3. CH_WIDTH must be smaller than BUS_WIDTH or same. 
 
  

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-12  
14.5.1.3 CS_REGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x000C, Reset Value = 0x1 
Name Bit Type Description Reset Value 
NCS_TIME_COUNT [9:4] RW NSSOUT inactive time = ((nCS_time_count + 3)/2) 
 SPICLKout 0 
RSVD [3:2] –=oeserved==–=...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-13  
14.5.1.4 SPI_INT_ENn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0010, Reset Value = 0x0 
Name Bit Type Description Reset Value 
INT_EN_TRAILING [6] RW 
Interrupt Enable for trailing count to be 0  
0 = Disables interrupt 
1 = Enables...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-14  
14.5.1.5 SPI_STATUSn (n = 0 to 4)  
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0014, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_DONE [25] R 
Indication of transfer done in Shift register (master 
mode only) 
0 = All case except Tx FIFO...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-15  
14.5.1.6 SPI_TX_DATAn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0018, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_DATA [31:0] W This field contains the data to be transmitted over 
the SPI channel. 0 
 
14.5.1.7 SPI_RX_DATAn...

Samsung Confidential  
Exynos 5250_UM 14 Serial Peripheral Interface 
 14-16  
14.5.1.9 PENDING_CLR_REGn (n = 0 to 4) 
 Base Address: 0x12D2_0000 (SPI0) 
 Base Address: 0x12D3_0000 (SPI1) 
 Base Address: 0x12D4_0000 (SPI2) 
 Base Address: 0x131A_0000 (ISP-SPI0) 
 Base Address: 0x131B_0000 (ISP-SPI1) 
 Address = Base Address + 0x0024, Reset Value = 0x0 
Name Bit Type Description Reset Value 
TX_UNDERRUN_CLR [4] RW 
TX underrun pending clear bit 
0 = Non-Clear 
1 = Clear 
0 
TX_OVERRUN_CLR [3] RW 
TX...