Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-28  
  FUARTCLK = baudrate  16 
 
 This allows sufficient time to write the received data to the receive FIFO. 
 
  

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-29  
12.6.1.13 UINTPn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0030, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
MODEM=[3]=RW=Generates Modem interrupt=0=
TXa=[2]=RW=Generates...

Samsung Confidential  
Exynos 5250_UM 12 Universal Asynchronous Receiver and Transmitter 
 12-30  
12.6.1.15 UINTMn (n = 0 to 4) 
 Base Address: 0x12C0_0000 (UART0) 
 Base Address: 0x12C1_0000 (UART1) 
 Base Address: 0x12C2_0000 (UART2) 
 Base Address: 0x12C3_0000 (UART3) 
 Base Address: 0x1319_0000 (ISP-UART) 
 Address = Base Address + 0x0038, Reset Value = 0x0000_0000  
Name Bit Type Description Reset Value 
RSVD [31:4] –=Reserved=0=
MODEM=[3]=RW=Mask Modem interrupt=0=
TXa=[2]=RW=Mask Transmit...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-1  
13 IIC-Bus Interface 
13.1 Overview 
The Exynos 5250 RISC microprocessor supports four multi-master I2C-bus serial interfaces. To transmit 
information between bus masters and peripheral devices connected to the I2C-bus, a dedicated Serial Data Line 
(SDA) and a Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional. 
In multi-master I2C-bus mode, multiple Exynos 5250 RISC microprocessors receive or transmit serial...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-2  
Figure 13-1 illustrates the I2C-bus block diagram. 
 
    Figure 13-1   I2C-Bus Block Diagram 
 
 
 PCLK
Address Register
SDA4-bit Prescaler
I2C-Bus Control Logic
I2CSTATI2CCON
Comparator
Shift Register
Shift Register(I2CDS)
Data Bus
SCL
   

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-3  
13.2 Features 
 9-channels Multi-Master, Slave I2C-bus interfaces   
(8-channels for general purpose, 1-channel for HDMI dedicated) 
 7-bit addressing mode 
 Serial, 8-bit oriented, and bi-directional data transfer 
 Supports up to 100 kbit/s in the Standard Mode  
 Supports up to 400 kbit/s in the Fast Mode 
 Supports Master Transmit, Master Receive, Slave Transmit and Slave Receive operation 
 Supports Interrupt or Polling...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-4  
13.3 IIC-Bus Interface Operation  
The Exynos 5250 I2C-bus interface has four operation modes:  
 Master Transmitter Mode 
 Master Receive Mode 
 Slave Transmitter Mode 
 Slave Receive Mode 
The functional relationships among these operating modes are described in this section.  
 
13.3.1 Start and Stop Conditions 
When the I2C-bus interface is inactive, it is usually in Slave Mode. In other words, the interface should be in Slave...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-5  
13.3.2 Data Transfer Format 
Every byte placed on the SDA line should be 8 bits in length. There is no limit to transmit bytes per transfer. The 
first byte that follows a Start condition should contain the address field. W hen the I2C-bus is operating in Master 
Mode, the master transmits the address field. Each byte should be followed by an acknowledgement (ACK) bit. 
The MSB bit of the serial data and addresses are sent first....

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-6  
13.3.3 ACK Signal Transmission 
To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse 
occurs at the ninth clock of the SCL line. Eight clocks are required for the 1-byte data transfer. The master 
generates clock pulse that is required to transmit the ACK bit. 
The transmitter sets the SDA line to High to release the SDA line when the ACK clock pulse is received. The 
receiver drives...

Samsung Confidential  
Exynos 5250_UM 13 IIC-Bus Interface 
 13-7  
13.3.4 Read-Write Operation 
When data is transmitted in Transmitter Mode, the I2C-bus interface waits until I2C-bus Data Shift (I2CDS) register 
receives the new data. Before the new data is written to the register, the SCL line is held Low. The line is released 
only after the data has been written. Exynos 5250 holds the interrupt to identify the completion of current data 
transfer. After the CPU receives the interrupt request, it...