GE Cardiocap 5 Service Manual

							
Frames and Software 
A CPU control signal (ICHGLOW) reduces the maximum charge current. This can be used momentarily 
to cut the power consumption peaks of the monitor.  
Battery connector (X4) 
PIN  SIGNAL/VOLTAGE I/O DESCRIPTION 
X4/1 BAT in Battery voltage 
X4/2 BAT in  
X4/3 GND   
X4/4 GND   
5.4.8 Control electronics 
The main functions of the control and measuring electronics are listed below: 
• Buffering between CPU and DC/DC board signals. 
The buffers are HCT logic to be able to accept both 5V and 3.3V logic levels in their inputs. The 
output is 5V cmos level.  
• Power-on logic.  
Pushing the on/stby switch to on position causes +3.3V and +5V supplies to rise. (+3.3V and 
+5V on and off sequence: +3.3V rises first and goes off last.) The CPU controls the other power 
supplies. Pushing the on/stby switch to standby position does not directly disable the supply 
voltages. The switch position information is wired also to the CPU, which controls the power 
supplies’ switching off, also +5V and +3.3V supplies.  
• Over-voltage detection. 
+5V and +3.3V are rapidly pulled down by a crowbar circuitry in case of over-voltage. All the other 
power supplies are disabled. Over-voltage in +15VB causes VDD to be switched off by signal 
VDD_SHUTDOWN/. Over-voltage information goes also to the CPU by signal OV_15VB/.  
• VDD detection and over-temperature detection (signal VDD/TEMP_OK).  
• Monitor internal temperature measurement (signal TEMP to A/D converter).  
• Battery voltage measurement (signal BATVOLT to A/D converter). 
Low-battery detection. On battery use a too-low battery voltage causes all power supplies to be 
switched off without CPU control (HW limit). The purpose of this is to prevent the battery from 
overdischarging in case of CPU control malfunction.   
• Switching off all power supplies in over-temperature condition by the CPU.  
• Switching a power-resistor load to the battery to enable the CPU to measure approximate 
capacity of the battery.  
• The high-charge states of the battery charger are indicated to the CPU by signal CHG_ON/.  
• Controlling Cardiocap/5’s front panel charge LED. 
When the charger is in high-charge states (that is, not in the float charge) the LED is flashing. 
When in the float-charge state, the LED is continuously lit, indicating a fully charged battery. 
During battery use, the LED is off indicating there is no charging.  
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CPU connector (X7) 
PIN  SIGNAL I/O DESCRIPTION 
X7/1 ON/STBY_1 in STBY switch end 1 
X7/2 GND  STBY switch end 2 
X7/3 STOP/ in Shut +3.3V and +5V switchers 
X7/4 POW_WD in Watchdog refresh 
X7/5 EN_VIN12V in Enable VIN_12V 
X7/6 EN_12V in Enable +12V 
X7/7 EN_15VB in Enable VIN_15VB and boost conv. 
X7/8 EN_15V in Enable +/-15V switcher 
X7/9 EN_15VD in Enable +15VD circuit breaker 
X7/10 CHG_INH in Disable charger input v. VCHG 
X7/11 BAT_TEST in Connect battery test load 
X7/12 VCONTRAST in ADCH10, scaled to 0 to 5V 
X7/13 RESET/ in +3.3V and +5V reset from CPU 
X7/14 ICHGLOW in Reduce battery charge current 
X7/15 FAN_ON in Enable VFAN 
X7/16 OC_15VB/ out Boost converter over-current 
X7/17 OC_15VD/ out +15VD over-current 
X7/18 OV_15VB/ out +15VB over-voltage 
X7/19 CHG_ON/ out Battery high-charge on 
X7/20 CHG_LED out Charge LED control 
X7/21 VDD/TEMP_OK out VDD detect / TEMP o.k. 
X7/22 ADC_CS/ in A/D converter chip select 
X7/23 SSCLK in Serial data clock 
X7/24 SSDOUT in Serial data in (from CPU) 
X7/25 SSDIN out Serial data out (to CPU) 
X7/26 NC_1  Not connected 
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5.4.9 AD converter 
The analog-to-digital converter is controlled by the CPU via a slow serial data bus. The signals are 
SSCLK (clock), SSDOUT (CPU data out), SSDIN (CPU data in), and ADC_CS/ (chip select). The A/D 
converter is an 11-channel, 12-bit circuit. It uses external reference voltage. On the DC/DC board, the 
reference voltage is RC-filtered from +5V_INT supply. The input voltage range is 0 to +5V. 
A/D channels 
CHANNEL SIGNAL/VOLTAGE DESCRIPTION 
ADCH0 VDD/BAT  
ADCH1 VIN_15VB  
ADCH2 VDD  
ADCH3 +12V  
ADCH4 +15VD  
ADCH5 +15V  
ADCH6 -15V  
ADCH7 +2.5VREF  
ADCH8 TEMP Temperature signal 
ADCH9 BATVOLT Battery voltage signal 
ADCH10 VCONTRAST Reserved for future use 
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Cardiocap/5 Technical Reference Manual 
5.5 CPU board 
The CPU board performs central data processing of the Cardiocap/5 monitor. The CPU board is based 
around an embedded AMD ELAN SC 410 (66MHz) processor. The memory chips listed below are 
located on the CPU board: 
• 16MByte DRAM 
• 8MByte Code Flash 
• 8MByte Store Flash 
• 2Mbyte Boot Flash 
• 32kByte NV-SRAM 
 
Figure 5-8. The CPU board 
The CPU board manages power by controlling and monitoring the voltage levels and power 
consumption of the monitor. It shuts off supply voltages if over-current is detected. 
The CPU board controls the Digital and Analog I/O, Serial Data interface, and Ethernet interface. In 
addition to the external interfaces, the CPU controls the internal Module Bus and Recorder interface. A 
Watchdog on the CPU board monitors the operation of the software. 
The ComWheel and Matrix keyboard are directly connected to the CPU board. The Real-Time Clock, 
Audio generator, and Display controller are located on the CPU board. The CPU board is also equipped 
with two PCMCIA-compatible data-card slots for software loading and data transfer purposes. 
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DRAM
2 x 4Mx16
code & data
AMD ELAN   SC 410  ( 66MHz)
       - 486 core + 8kbyte cache
       - DRAM controller
       - 3 x Timer/Counter
       - 1 x UA RT(IrDA)
       - 2 x Interrupt Controller
       - DMA  Controller
       - ISA & VL-Bus
       - Digital I/OCrystal
32kHz
IrDAJTAG test
connector
256k x 16 display
memory
 1x
PCMCIA
connector LCD
Addr &
RAS &
CAS
Mem
card 2
Digital
I/O
Mem
card 1PCMCIA
controller
Data_lo
Data_hi
STR ATA FLASH 4M x 16
code       PLD
- upi
- keyboard
- comwheel
- ssio interface
- audiogen
- addr decode
- 3v bus buffer r4x4 matrix KB
5V DATA
 BUS
PLD
serial
EPROM Device Link4 x 8 bit
DAC Brightness
Contrast
Audio
Ethernet ID
 FILE FLASH
2M x 16
Warmstart & Boot
R TCLK + SRAM
32K x 8
NV-SRAM 10BASE-T
ComWheel
4 x 8 bit DAC Recorder
Serial I/O 1
Serial I/O 2CTRLPC-interface
PC-keyboard
Module Bus
SSIO
ADDR
VGA
controller
Ethernet
controller
If the CPU supports 
Network functionality
 
Figure 5-9. Block diagram of the CPU board  
						

							
Cardiocap/5 Technical Reference Manual 
5.5.1 Synchronous serial communication 
The CPU board contains two separate synchronous serial channels. Channel one handles 
communication with the Ethernet ID-block (if available). Channel two is the internal serial bus of the 
monitor. 
The synchronous serial channels are implemented with PLD to minimize the load of the main 
processor. Communication with the chips connected to the bus is handled by the PLD registers. 
Ethernet ID-block 
The Ethernet ID-block can be connected to the 9 pin D-connector on the monitor’s rear panel. It 
contains an EPROM chip where the bedside specific ID number has been stored. The processor will 
read the ID number with PLD by sending the address of the memory location to the chip. 
Internal synchronous serial bus 
The following chips are connected to the internal synchronous serial bus: 
• 8 bit x4 DAC 
• 12 bit x4 DAC 
• 12 bit x11 ADC 
Only the 8 bit x4 DAC is located on the CPU board. It generates audio signals and controls the 
brightness and contrast of the display. 
The 12 bit x4 DAC on the I/O board drives the Analog Output signals. 
The 12 bit x11 ADC on the DC/DC board monitors the internal parameters of the monitor, such as 
voltages, charging currents, and temperatures. 
5.5.2 Asynchronous serial channels 
There are three different asynchronous serial channel groups on the CPU board: 
• Serial channel implemented with PLD:  Module Bus 
• Serial channels of the Quart:  
Computer Interface 
Recorder Interface 
Serial_I/O_1 (not in use) 
Serial_I/O_2 (not in use) 
• Serial channel integrated in Elan:  Reserved for future purposes 
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Serial channels implemented with PLD (D19) 
Module Bus 
PLD and Main Software control the function of the Module Bus and the Universal Peripheral Interface 
(UPI). This way the interrupts generated by the serial communication will not load the main processor. 
The Module Bus Reset comes from PLD pin 105. 
The Module Bus is buffered to RS-485 level on the CPU board. The baud rate of the Module Bus is  
500 k baud. 
Serial channels of the Quart 
Recorder interface 
The Recorder serial interface channel uses both CTS# and RTS# handshake signals. In addition there 
is a reset signal for the recorder.  
The Recorder serial channel has been implemented on channel D of Exar’s UART ST16C654. The baud 
rate is 76.8 k baud. 
Computer Interface 
The Computer Interface serial channel is buffered to RS-232 level on the I/O board. It can be used for 
interfacing some external device to the monitor. The computer interface is using channel A of Exar’s 
UART ST16C654. 
Serial I/O 
The channels B and C of Exar’s UART ST16C654 have been reserved for future purposes. They have 
been wired to the I/O board connector on the CPU board. 
5.5.3 Keyboards and ComWheel 
Keyboard interface 
An external keyboard can be connected to the monitor through the keyboard interface bus. 
A PLD provides clocking for the bus and controls transmission and receipt of the messages. The 
keyboard interface is a synchronous serial bus. The buffering of the bus takes place on the I/O board. 
Matrix keyboard 
The 4x4 matrix keyboard has been implemented with a PLD. One row at a time is set active “0” and 
after that the state of each column is read. The state of the column is “0” if the button corresponding 
to that row and column is pressed. 
ComWheel 
Two pulse generators on the ComWheel change their states in turn when the wheel is rotated. The 
direction of rotation is defined by comparing the current state to the previous one. The PLD reads the 
state of the ComWheel and generates the I/O_INT interrupt if the state of the ComWheel has changed. 
The ComWheel push switch is connected to the matrix keyboard. 
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5.5.4 Digital I/O signals 
The different I/O-signals have been split into groups according to their function:  
• Defibrillator synchronization output. 
• Alarm signals. 
• PWR-board control signals. 
Defibrillator synchronization output  
Each detected QRS complex generates a 10 ms long, 5V pulse to pin 3 of the rear panel 44-pin I/O 
connector. 
Alarm signals 
In addition to audible alarms, the CPU board drives the Alarm LEDs on the monitor front panel and a 
NURSE_CALL signal on 44-pin I/O connector pin 5. The processor’s I/O pins directly drive the Alarm 
LEDs. The PLD generates the NURSE_CALL signal, which is in high state when the alarm is active. In 
addition to the digital nurse-call signal, floating relay contacts are available on pins 11 and 12. The 
relay located on the I/O board connects the pins when the nurse-call signal is active. 
Power supply board control signals 
The control signals for the DC/DC board come directly from the processor’s I/O-pins: 
X5 pin Signal name Function 
3 STOP# Shut off +3.3V and +5V switchers 
4 POW_WD Watchdog refresh 
5 EN_VIN12V Enable VIN_12V 
6 EN_12V Enable +12V 
7 EN_15VB Enable +/- 15V circuit breaker 
8 EN_15V Enable +/- 15V switcher 
9 EN_15VD Enable +/- 15VD circuit breaker 
10 CHG_INH Disable charger input v. VCHG 
11 BAT_TEST Connect battery test load 
13 PWR_RESET +3.3V and +5V reset disables all other control signals from CPU board to 
power supply boards 
14 ICHG_LOW Reduce battery charge current 
16 FAN_ON Enable VFAN 
The interrupts generated by the DC/DC board come directly to the processor’s I/O pins: 
X5 pin Signal name Function 
16 OC_15VB# Boost converter over-current interrupt 
17 OC_15VD# +15VD over-current interrupt 
18 OV_15VB# +15VB over-voltage interrupt 
19 CHG_ON# Battery high-charge on 
21 VDD/TEMP_OK VDD detect/Temp OK 
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5.5.5 Display controller 
The display controller chip is a VGA-compatible chip 65550. Two 256k x 16 display memories 
connected to the display controller enable use of a 32-bit databus for addressing display memory. The 
display controller is directly connected to the VESA Local bus (VL-Bus) of the processor. 
In addition to the control signals, the supply voltages (VEE_S & V_DISP) for the display are available 
on the display connector X7. The supply voltages for the display must be connected ON and OFF in a 
certain order compared to the control signals. The display-controller chip controls voltage sequencing. 
Display brightness is adjusted with channel D of the 8-bit DAC. The DAC output drives the brightness-
control circuit located on the Backlight board. 
The voltage level for the display can be selected with jumper X14.  
Jumper X14 V_DISP Signal level 
1 - 2 +5.0V CMOS 
2 - 3 +3.3V TTL 
5.5.6 Memory 
DRAM 
The CPU board contains two parallel 16 x 4M DRAM chips. The supply voltage for the chips is 3.3V. 
When starting the monitor, the program code is loaded into the DRAM from the FLASH memory as the 
DRAM memory is much faster than FLASH memory, which is used as a code storage. 
When switching off the monitor, the contents of the memory area reserved for the variables is copied 
to the FLASH memory (8Mbyte). This way the data needed for the Warm Start is easily stored. 
To define if there should be Warm or Cold Start, the elapsed time since the last switch OFF is checked 
when the monitor is switched ON. Depending on the elapsed time, data is loaded either from the Store 
Flash or from the Code Flash. 
An ELAN SC 410 processor generates the signals needed for controlling the DRAM chips. 
FLASH 
FLASH memory is used for three different purposes: 
• Code Flash D10 
Code Flash reserves 8 Mbyte of memory. New program can be loaded into that chip from the 
PCMCIA card. 
• Store Flash D9 
This is “Warm Start” memory used to store the contents of the DRAM memory area reserved for 
the variables when switching off the monitor. 
• Boot Flash D9 
The Boot Flash means that the uppermost block of D9 memory area is reserved for the Boot code. 
The contents of the Boot Flash block cannot be changed without connecting the board to the 
factory testing device. 
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5.5.7  PC and ethernet interfaces 
PC card 
The PC card interface, a Cirrus PCMCIA controller CL-PD6722, drives two PC cards. It is connected to 
the ISA bus of the processor. 
The PC-Card interface accepts standard +3.3 V or +5  V cards. The controller selects the correct voltage 
automatically. A separate VCC and VPP switchin g matrix connects the voltage to the cards. 
Ethernet 
There are two different CPU boards available: one supporting the Network functionality and another 
not supporting it. The CPU supporting the Network functionality has all the needed components 
attached to the board. 
The Ethernet controller, a National DP83907, is  connected to the ISA bus of the processor. The 
10BASE-T (paired cable) Ethernet inte rface meets the IEEE802.3 standard. 
5.5.8 Audio 
Values corresponding to audio waveforms are programmed in PLD memory for generating the audio 
signals. The values are fed at the desired sp eed to a Texas 8-bit DAC converter (TLC5620). 
DAC channel A generates the audio waveform and channel B adjusts the volume. The frequency range 
of the audio generator is 70Hz - 2500Hz.  
The output amplifier is located on the I/O board. 
5.5.9 Real-time clock  and battery back-up RAM 
An SGS-Thomson M48T35 chip containing 32k*8 RAM  is used as a Real-Time Clock (RTC) on the CPU 
board. A lithium battery located on the chip is us ed to backup data stored in the RAM. The RTC 
integrated in the chip runs on the same battery.  The battery runs the chip only in case the power 
supply voltage is less than 3V. The battery lifetime is approximately 10 years. 
5.5.10  Control circuit (D24) 
Supply voltage control 
The control circuit MAX 705 watches  the +3.3 V and +5 V supply voltages and resets the CPU board in 
case the voltages do not remain within allowed limits. 
Watchdog function 
The processor’s I/O pin IO_CS14 is connected to th e Watchdog input of MAX 705. If the state of the 
pin does not change at one-second interval s, the control circuit resets the board. 
The purpose of the watchdog is to restart the monitor  if there is a serious malfunction. This feature is 
necessary in two cases: 1) when  the main CPU’s software is not able to control the monitor and  
2) when the software controls the moni tor but detects a serious malfunction.