ATT System 25 Reference Manual

							FUNCTIONAL DESCRIPTION
Tip Ring Line (ZTN78)
The Tip Ring Line Circuit Pack interfaces eight analog tip and ring voice terminal lines
(single-line voice terminals) and the TDM bus.Figure 3-17 shows the Tip and Ring Line
unique circuitry.The TN742 can be used instead of the ZTN78 Tip Ring CP. The TN742
supports up to five bridged single-line voice terminals; however, only two can be off-hook at
one time.The ZTN78 does not support bridged terminals.In addition, the TN742 supports
out-of-building, extended, and off-premises stations, while the ZTN78 does not. The ZTN78
supports only a 1.2 Ringer Equivalency Number (REN).
NPE 0
NPE 1
ON-BOARD
MICRO-
PROCESSOR
POWER
SUPPLY
Figure 3-17.
l Ringing Application CircuitTip Ring Line (ZTN78) Unique Circuitry
TOANALOG
TIP/RING
TERMINALS
This circuit receives ringing voltage from the power supply. It monitors ringing
voltage and current and generates signals to the on-board microprocessor indicating
zero ringing voltage and current. It also detects when a terminal user has lifted the
receiver during ringing preventing the application of ringing to the terminal’s handset
receiver.
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							FUNCTIONAL DESCRIPTION
l Port I/O Circuit
This circuit includes bus expanders connecting the on-board microprocessor and the
port circuits.It receives commands from the on-board microprocessor and
distributes them to the individual port circuits.It also accesses the port circuit scan
points and passes the information to the on-board microprocessor.
l -48 V To -24 V Power Conditioner
This circuit converts -48 V power from the power supply into a conditioned source of
-24 V power for the electronic battery feed circuits.
l Eight Port Circuits
Each port circuit is identical.A port circuit consists of a coder/decoder (codec),
hybrid circuit, battery feed circuit, and ring relay.
The codec is a 4-wire circuit that converts the NPEs output to an analog signal.
Likewise, it converts the analog signal from a central office trunk to a PCM data
signal to the NPE. The hybrid circuit converts the codec 4-wire analog signal to a 2-
wire analog signal that is connected to the central office trunk by the line
transformer.
The battery feed circuit provides talking battery to the voice terminal. It also detects
when a receiver is lifted, and provides the message waiting signal by periodically
reducing the feed voltage to zero.
The ring relay provides the interface between the ringing application circuit and the
port circuit. It causes ringing to turn on and off.
System Resources
The System Resource Circuit Packs (CPS) are the Service Circuit Clock (ZTN131), the Tone
Detector (TN748B), and the Pooled Modem (TN758).
Service Circuit Clock (ZTN131)
The Service Circuit CP (Figure 3-18) provides the clock signals of the system and generates
and receives tones. It provides four touch-tone receivers, generates all tones for the system,
and supplies the system clocks.The ZTN131 can support up to 75 Dual Tone
Multifrequency (DTMF) dialers depending on call traffic; the TN748Bs might be required in
heavy traffic situations, even with less than 75 DTMF dialers. Each System 25 must contain
one Service Circuit CP.Power for the circuit pack (+5 volts dc) is provided on the
backplane. The Service Circuit has the following unique circuitry:
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							FUNCTIONAL DESCRIPTION
l
lBus Buffers
There are four bus buffers on the circuit pack. The clock driver and receive buffers
interface three system clock signals (2.048 MHz, 8 kHz, and 160 kHz) to the TDM
bus. Two buffers interface the system tones (see Table 3-A) between the TDM bus
and the Service Circuit CP. Music is not provided by the Service Circuit but can be
provided via a port interface on a Tip Ring Line CP (ZTN78).
SAKI
This circuit functions the same as in the SAKI in the common circuitry for the
intelligent port circuits.
Figure 3-18.Service Circuit (ZTN131)
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							FUNCTIONAL DESCRIPTION
l On-Board Microprocessor With External RAM
This circuit functions the same as the microprocessor in the common circuitry for the
intelligent port circuits.In addition, it tells the dual-port RAM in the time slot table
circuit the appropriate time slots in which to place a tone. The external RAM also
has work space for complex tones (i.e., those tones that vary with time).
l Clock Circuit
The clock circuit consists of a 20.48-MHz oscillator, various dividers, and shift
registers. The clock circuit runs independently from the rest of the Service Circuit
circuitry. The clock circuits start running when the circuit pack is first powered up
and is not controlled by the on-board microprocessor.
The output of the 20.48-MHz oscillator is fed to the clock divider. The divider divides
by 10, 2560, and 128. These circuits produce the 2.048-MHz, 8-kHz, and 160-kHz
clock signals, respectively.The clock generator feeds these signals to the clock
driver/receiver bus buffer and the tone clock.The tone clock uses these signals to
synchronize the counters in the tone generator and time slot table circuits with the
TDM bus.
l Tone Generator
The tone generator consists of a digital signal processor (DSP), a counter, and a
dual-port tone RAM. The DSP operates at 10 MHz and produces 24 different tones.
The dual-port tone RAM stores these tones in 24 different addresses. The counter
under control of the tone clock causes the DSP to transmit one sample of each tone
every 8-kHz. The counter is synchronized to the TDM bus and is offset to provide
delay needed for access time.
l Time Slot Table and Counter
The time slot table consists of a dual-port time slot table RAM and a counter. The
dual-port RAM (DPRAM) contains 256 different addresses. These addresses
correspond to the time slots on the TDM bus. The counter sequences through the
time slot table addresses in the dual-port RAM and causes the proper tone(s) to be
output by the dual-port tone RAM on TDM bus time slots.
l Tone Detector Ports
The Service Circuit CP provides four Dual Tone Multifrequency (DTMF) detector port
circuit interfaces via the TDM bus. Each port circuit is connected to an NPE serial
input and output.Ports 0, 1, 2, and 3 are DTMF tone detectors with NPE loop-
around paths.
The four port circuits contain a DSP, NPE to DSP interface circuitry, a DSP restart
circuit, and an interrupt generator. One DSP implements two tone receivers.
The TDM bus signals are connected to the DSP in serial form from the NPEs by the
DSP interface circuit. The DSP controls the output clocking of the NPE. The system
framing signal is synchronized and connects to the DSP.
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							FUNCTIONAL DESCRIPTION
lPort I/O and Sanity Check Circuit
This circuit interfaces the on-board microprocessor to the port circuits and checks
the sanity status of the DSPS of the port circuit.
Tone Detector (TN748B)
The Tone Detector Circuit Pack provides four touch-tone receivers and two general purpose
tone receivers that detect appropriate system and network tones on the TDM bus. The Tone
Detector CP consists of the same common circuitry as the intelligent port circuits plus the
unique circuits shown in Figure 3-19. The system can have a maximum of two Tone
Detector CPs.
TDM
BUS
LEADS
CIRCUIT
PACK
ADDRESS
LEADS
Figure 3-19.Tone Detector (TN748B)
lPort I/O and Sanity Check Circuit
TOUCH-TONE
PORTS
GENERAL
PURPOSE
TONEDETECTOR
PORTS
This circuit interfaces the on-board microprocessor to the port circuits and checks
the sanity status of the port circuits Digital Signal Processors (DSPs).
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							FUNCTIONAL DESCRIPTION
l Port Circuits
There are eight port circuits.
Six port circuits are connected to Network Processing
Elements (NPEs). Port circuits 0, 1, 4, and 5 are DTMF tone detector ports. Each of
the six port circuits has an associated Digital Signal Processor (DSP), NPE to DSP
interface circuitry, a DSP restart circuit and an interrupt filter. Port circuits 2 and 6
are general purpose tone detector ports.Port circuits 3 and 7 provide digital loop-
back testing of each NPE on the circuit pack.
The NPE serializes TDM bus signals that are connected to the DSP in serial form
from the NPEs by the DSP interface circuit.
Serial clock and data signals connect
directly from the NPE to the DSP. The system framing signal is synchronized and
connects to the DSP.
The DSP restart circuit controls the DSPs. When the on-board microprocessor is not
functioning properly, the DSP restart circuit takes all of the DSPs out of service. It
restarts each individual DSP under control of the port I/O and sanity check circuit.
The touch-tone DSPs, under control of the on-board microprocessor, write data
synchronously to the NPEs.The interrupt filter detects valid touch-tone signals and
allows end-to-end transmission while blocking end-to-end touch-tone signaling.
Pooled Modem (TN758)
The Pooled Modem Circuit Pack supports 0-300 and 1200 bits per second (bps) data speeds
and provides the following:
l Circuitry to provide a signal compatible with the modulation formats of the 212-series
modems
l Modem emulation (see below)
CapabilityData Module Mode
0-300 AsynchronousLow
300 Asynchronous300 Asynchronous
1200 Asynchronous
1200 Asynchronous
l Modem control functions corresponding to 212A-series modem operations.
A maximum of two Pooled Modem CPs are allowed in a single cabinet (six in a 3-cabinet
system).
The Pooled Modem CP (Figure 3-20) consists of common circuitry and two conversion
resources.The conversion resource (port) allows communications between two dissimilar
endpoints. For example, the Pooled Modem CP enables a digital data endpoint linked to an
ADU connected to a port on the Data Line CP (TN726) to communicate with either a local
analog data endpoint, such as a personal computer with a modem, or a remote host via a
CO trunk connection. Each port has two connections to the TDM bus: one to the digital
data endpoint via an ADU data module, and the other to an analog endpoint.
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							FUNCTIONAL DESCRIPTION
TDM
BUS
LEADS
CIRCUIT
PACKADDRESS
LEADS
Figure 3-20.Pooled Modem (TN758)
l Common Circuitry
The Pooled Modem contains the same common circuitry as port CPs.
l Conversion Resources
The two conversion resources (port circuits) are identical and each contain the
following:
— Microprocessor
— Transmit and Receive I-channel Controller (TRIC)
— Universal Synchronous/Asynchronous Receiver and Transmitter (USART)
— Data USART Clock (DUCK)
— Digital Signal Processor (DSP).
The microprocessor controlsan on-board data module and modem.
This
microprocessor communicates with the port circuit microprocessor over a serial
control channel.This channel allows the on-board microprocessor to send
messages to the port circuit microprocessor specifying call startup information,
option settings,information requests,various test modes, and call termination
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							FUNCTIONAL DESCRIPTION
information.It also allows the port circuit microprocessor to inform the on-board
microprocessor of various port circuit status information.
The DUCK and TRIC interface I-channel information between the port circuit and the
remote data module. The microprocessor controls the operation of the DUCK and
the TRIC by programming their internal registers. The DUCK and TRIC together
recreate the clock and serial data stream from the remote data module, and process
an on-board clock and serial data stream for delivery to the remote data module.
Control information, handshaking, and RS-232 control leads is passed between the
port circuit microprocessor and the remote data module by the TRIC.
The USART interfaces the serial data stream of the DUCK to the conversion
microprocessor.The USART can be programmed by the microprocessor to operate
synchronously or asynchronously. The USART also does the following tasks for the
port circuit microprocessor:
— Appends start and stop bits to parallel data received from the microprocessor
in the asynchronous mode
— Converts serial data received from the DUCK to parallel data
— Buffers data in both directions
— Detects and generates break characters.
The DSP provides modem emulation.It interfaces the port circuit signal and the
remote modem.The microprocessor directs the DSP to execute one of many
programs.The DSP produces data, carrier detection, and timing information for the
port circuit microprocessor.
DS1 Interface (TN767)
The DS1 Interface Circuit Pack provides connection capability to a 1.544 Mbps DS1 facility.
This DS1 facility is able to provide a communication link for 24 separate and independent
trunks. Each trunk provides a 64 kbps data transmission service for a DS1 Voice Grade tie
trunk. The circuit pack can also provide bit-oriented signaling on a per trunk basis.
Supported trunks include; automatic, immediate-start, delay-dial, and release-link trunks. The
circuit pack performs robbed-bit signaling using CO, TIE, DID, or OPS signaling protocol in
any remaining ports on a per port basis. The following lead appearances are provided on
the circuit pack: LBACK2, LBACK1, LO, LO (high), LI, LI (high).
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							FUNCTIONAL DESCRIPTION
Software
The System software consists of switched services,administrative, and maintenance
software. This software runs on top of the real-time operating system software.
Switched Services Software
The switched services software provides voice and data call processing. This software
resides in the Common Control circuitry and in the 8-bit on-board microprocessors located in
the port and service circuits.
The switched services software uses the operating system to provide a process based,
message passing,execution environment.The operating system scheduler provides
scheduling for the software according to process priority.
Administrative Software
The administrative software provides the control for system rearrangement and change via
the System Administration Terminal (SAT). This software resides in the CPU/MEM Circuit
Pack and does the following functions:
l Organizes the translation data for administrable entities in the system in a form that
can be viewed and changed at the System Administration Terminal.
l Tests entered data for consistency with data previously entered in order to avoid
such errors as the assignment of the same extension number to two voice terminals.
An erroneous or inconsistent data entry is disallowed and an error message is
provided.
l Causes the translation data to be downloaded, on command, to an optional Digital
Tape Unit (DTU).
Maintenance Software
The maintenance software provides automatic periodic testing of maintenance objects within
the system as well as consistency tests among the call status tables within the system. In
addition, demand testing is initiated when the system detects a condition requiring a need for
testing. Software tables are provided for storing error records. The records can be
accessed by maintenance personnel via the SAT.A Permanent System Alarm (a serious
error) causes an alarm indicator on the attendant console to light and an error record to be
stored in the error table.
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							FUNCTIONAL DESCRIPTION
Memory Allocation
The system software, like the hardware, is identified by release and version number. Each
version identifies a particular memory configuration for the release number. Main memory is
located in the Common Control circuitry, that is, the CPU/MEM Circuit Pack.
Real-Time Constraints
Real-time constraints are a function of the speed of the common control circuitry and the
traffic load. The switch is designed so that many time-consuming and repetitious functions
are performed by processors in the port and service circuit packs, thus relieving the common
control circuits.
Traffic load, defined as the sum of static and dynamic loads, is a function of the number of
features that are executed, the frequency with which they are executed, the system
configuration,and the instantaneous (peak) call processing load. The configuration
contribution to load is known as dynamic load. The static load consists of maintenance and
audit routines.
Software Partitioning
As shown in Figure 3-21, System 25 software is comprised of various modules, each
supporting a particular process. Typical modules (referred to as tasks) include the following:
l Administration
l Station Call Processing
l Station Message Detail Recording (SMDR) Call Record Processing
l Trunk Call Processing
l Dial Plan Manager
l Event Timer
l Save/Restore (Administration function)
l Maintenance and Audit Functions.
Specific software tasks are associated with the memory and call processing portions of the
CPU/MEM, the TDM Bus, and the Port Circuits.
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