ATT System 25 Reference Manual

							Figures
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 3-14.
Figure 3-15.
Figure 3-16.
Figure 3-17.
Figure 3-18.
Figure 3-19.
Figure 3-20.
Figure 3-21.System 25 Digital Switch3-1
CPU/MEM (ZTN142) Circuitry3-3
TDM Bus Time Slot Generation (Not a Timing Diagram)                                                  3-6
TDM Bus—Three Cabinet System                                                                        3-8
Equipment Connections Via Circuit Pack                                                                3-10
Port Circuit Pack Common Circuitry
                                                              3-13
Analog Line (TN742) Unique Circuitry                                                 3-15
ATL Line (ZTN79) Unique Circuitry
3-17
Auxiliary Trunk (TN763) Unique Circuitry                                                 3-19
Data Line (TN726) Unique Circuitry                                                        3-20
DID Trunk (TN753) Unique Circuitry                                       3-22
Ground Start Trunk (ZTN76) Unique Circuitry                                                         3-23
Loop Start Trunk (ZTN77) Unique Circuitry
               3-24
MET Line (TN735)Unique Circuitry                                                         3-25
Tie Trunk (TN760B) Unique Circuitry                                                         3-28
Tie Trunk (TN760B) Circuit Pack Option Switches                                                             3-28
Tip Ring Line (ZTN78) Unique Circuitry                                                3-30
Service Circuit (ZTN131)
3-32
Tone Detector (TN748B)                                                         3-34
Pooled Modem (TN758)
3-36
System Software Partitioning 3-40
Tables
Table 3-A.TDM Bus Time Slots                                                                                                                             3-7
Table 3-B.Signaling Type Summary3-29
Table 3-C.TN760B Tie Trunk Preferred Signaling Formats                                                                        3-29
November 1995-iii- 
						

							FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
This section describes how the digital switch and the software of System 25 provide control and
switching.
Digital Switch
Figure 3-1 shows a block diagram of the System 25 digital switch. The basic switch hardware
consists of the following:
l Common Control
l Switching Network
—
—
—
COMMON
CONTROL
SWITCHING
NETWORK
Time Division Multiplex (TDM) Bus
Port Circuits
System Resource Circuits
CPU/MEM
TDM BUS
PORT
CIRCUITS
SERVICECIRCUITTONEDETECTORPOOLED
MODEM
TRUNKS, VOICE,
AND DATA TERMINALS
Figure 3-1.
SYSTEM RESOURCES
System 25 Digital Switch
November 19953-1 
						

							FUNCTIONAL DESCRIPTION
Common Control
The Common Control circuitry consists of a single ZTN142 CPU/MEM (Call Processing
Unit/Memory) circuit pack (CP).
CPU/MEM CP
The CPU/MEM runs the system feature code for the system and provides for the storage of
software associated with system operation. This CP is powered from the backplane by +5 and –5
volts. It also draws -48 volts from the backplane to drive the Emergency Transfer Unit. The CP,
shown in Figure 3-2, includes the following circuits:
l
l
l
l
lMicroprocessor
A 68010 16-bit microprocessor that executes call processing and data processing features.
This includes all maintenance, administration, testing, and reporting software.
Memory Management
Memory management separates the on-board Random Access Memory (RAM) into 1024
memory pages of 256 bytes each. Each page is read and write protected and generates
bus errors when violated.
On-Board Memory
On-board memory includes 1 Mbyte of Read Only Memory (ROM) containing the powerup
tests, the switch operating system, and the system operation software. In addition, there are
192k bytes of protected RAM containing writeable data storage for call processing. The
RAM is backed up by an on-board trickle-charge battery that maintains memory contents
for up to two months. Of the 192k RAM, 32k is dedicated to translation data. The remainder
is dedicated to call status data and the operating system message queues.
EIA Channels
Four asynchronous RS-232 EIA ports (1-4) are included to permit communication with an
administration terminal, a Station Message Detail Recording (SMDR) device, and a digital
tape unit. (The fourth port is reserved for future use.) Each port can support 300, 1200,
4800, or 9600 baud rates.
Network Controller
The network controller transmits control channel messages between the Call Processor and
the port circuits over the TDM bus. The controller also monitors system clocks. The
controller includes an 8-bit microprocessor that acts as a throttle passing messages
between the Call Processor and the port board microprocessors.
3-2November 1995 
						

							FUNCTIONAL DESCRIPTION
Figure 3-2. CPU/MEM (ZTN142) Circuitry
November 19953-3 
						

							FUNCTIONAL DESCRIPTION
All uplink messages from the port circuits are checked for consistency and passed to the
Common Control. The controller is the distribution control point for all downlink control
messages. It continuously scans, over the TDM bus, the port circuit microprocessors for
sanity and activity. External RAM associated with this microprocessor stores control
channel information and port related information.
The controller consists of bus buffers and a Sanity and Control Interface (SAKI). It also
contains a Digital Signal Processor (DSP) modem. The bus buffers provide the interface
between the TDM bus and the on-board data buses to the SAKI and DSP modem. The
SAKI receives and transmits control messages on the first five time slots on the TDM bus.
The DSP modem is a 1200-baud, answer-only modem for Remote Initialization and
Maintenance Service (RIMS) access. The microprocessor communicates with the SAKI, the
DSP modem, and external RAM over the address and data bus.
l Clock
A clock provides both time-of-day information (in seconds, minutes, and hours), and the
date to the 68010. The clock automatically adjusts for leap years. An on-board battery
backs up the clock, so that accurate time is maintained even when the system power is off.
l Interrupt Circuitry
Interrupts are prioritized into seven levels, of which the highest (level 7) is nonmaskable.
The interrupts are:
InterruptLevel
AC Fail
7
Work cycle6
Off board5
EIA ports 3 and 44
EIA ports 1 and 23
Off board2
Off board1
l Reset Circuitry
The processor is automatically reset when power is turned on, when the +5 volt power
supply drops below 4.5 volts (after it returns to +5 volts), or when the network controller
determines that the processor is not functioning correctly. The processor can also reset the
network controller when it determines that the network controller is not functioning correctly.
l Bus Error Circuitry
Bus errors suspend the processor from executing code. Bus errors are generated when
memory management detects illegal reads or writes to RAM, when the processor attempts
to access circuit packs or chips not physically present, or when the network controller
determines that the processor is not functioning correctly.
3-4November 1995 
						

							FUNCTIONAL DESCRIPTION
l Emergency Transfer Unit (ETU) Control
Removes -48 V dc power from the ETUs of the system when the system loses power
or a major system malfunction occurs.
l Bus Terminators
These resistors are required for proper operation of the TDM bus. The CPU/MEM
CP provides the proper termination for one end of the bus, and a plug-in TDM bus
termination circuit card (plugs into cabinet backplane) is used to terminate the other
end.For this reason, the CPU/MEM CP must always be located in slot #1 of
Cabinet 1.
3-5 
						

							FUNCTIONAL DESCRIPTION
Switching Network
System 25 uses distributed processing techniques to provide switched voice
services.The switch operates at 64 Kbps.The switching network consists of
Division Multiplex (TDM) bus, the Port Circuits and the System Resource Circuits.
The TDM bus connects the intelligent ports to the Common Control circuit packand data
the Time
and other
ports through the network control circuit.The system resource circuits provide tone
sources, receivers, detectors, and pooled modems.The intelligent ports connect external
communications facilities to the TDM bus.
TDM Bus
The TDM bus consists of two groups
matching grounds. The port circuit
(PCM)] signals on the bus.of eight signal leads and five control leads, each with
packs place digitized voice [pulse code modulated
The bus operates at 2.048 MHz. The framing pulse rate is 8 kHz. This provides 256 time
slots (0-255) on the bus.The time slots are 488 ns wide.Time slots are generated as
shown in Figure 3-3.The first five time slots are used for communications between the
Common Control, the intelligent port, and resource circuit packs.
SYSTEM FRAME8 KHZ
(125 MICROSECONDS)
488 NANOSECONDS—————————SYSTEM CLOCK
2.048 MHZ
TIME SLOTS O1234
52550
256 TIME SLOTS
Figure 3-3.TDM Bus Time Slot Generation (Not A Timing Diagram)
Two time slots are required for each 2-party conversation.Each party transmits (talks) on
one time slot and receives (listens) on another.Only five parties are allowed in a conference.
During a conference connection, each member of the conference transmits on an individual
time slot while receiving on as many as four other time slots. The actual switch capacity is
115 simultaneous 2-party conversations.
Table 3-A shows the allocation of the 256 time slots. Five are used for system control, 17
for tones, 232 for call processing, and two are not used.
3-6 
						

							FUNCTIONAL DESCRIPTION
l
lPhysical Characteristics
The TDM bus is an 8-bit bus that snakes continuously between cabinets in a
multicabinet system as shown in Figure 3-4. The total length is about 9 feet for a
three cabinet system.The bus is driven from any of the circuit packs in the cabinets.
Similarly, a signal on the bus can be received by any circuit pack.
Within a cabinet, the bus is printed on one side of the circuit pack carrier backplane
while the other side is solid ground.Ribbon cables are used to connect the TDM bus
between cabinets in a multi-cabinet system.
Electrical Characteristics
The TDM bus is an unbalanced, low characteristic impedance transmission line.
Paths printed over a ground plane on the carriers and the flat ribbon cables between
carriers maintain this impedance level over the full length of the bus.
One end of the bus is terminated to ground with a bus termination circuit card and
the other end is terminated by a network on the ZTN130 CPU/MEM CP. Each circuit
pack connects to the bus through a custom bus driver device. The bus driver is a
switchable constant current source so that even in the “high” output state there is no
bus loading to cause reflections. The current output of the drivers is adjusted so that
logic “high” is 1.5 volts compared to a “low” of 0 volts.
Table 3-A. TDM Bus Time Slots
Time Slot No.FunctionTime Slot No.Function
00-04Control (5)15941 Hz*
161209 Hz*
Tones (17)
171336 Hz*
05RIMS Listen
181447 Hz*
06RIMS Talk
191637 Hz*
07Dial Tone
20Data Null
08Busy Tone21Reorder Tone
09Ringback Tone
10Voice-Null22-253Flexible
11Music on Hold
(232)
12697 Hz*
13770 Hz*
254,255
Not used (2)
14
852 Hz*
* These tones are used to generate touch-tone signals.
3-7 
						

							FUNCTIONAL DESCRIPTION
TDM
BUS
TERMINATOR
CARD
TDM BUS
EXTENDER
CABLE
(CBC)
AC POWER
TO SINGLE
POINT GROUND
CABINET
ON/OFFSWITCH
3
AC POWER
# 6 AWGBUILDING
GROUND
WIRE
CABINET 2
AC POWER
#6 AWG
GROUND
WIRE
CABINET 1
COUPLED
BONDING
CONDUCTOR
Figure 3-4.TDM Bus - Three Cabinet System
3-8 
						

							FUNCTIONAL DESCRIPTION
Port Circuits
The port circuit packs listed below provide the link between trunks and external equipment and the
TDM bus. Figure 3-5 shows the equipment types that can be connected to the digital switch by the
call processing and port circuit packs.
Analog Line (TN742/TN746)Loop Start Trunk (ZTN77)
ATL Line (ZTN79)MET Line (TN735)
Auxiliary Trunk (TN763)STARLAN Interface (ZTN84)
Data Line (TN726)Tie Trunk (TN760B)
DID Trunk (TN753)Tip Ring Line (ZTN78)
Ground Start Trunk (ZTN76)DS1 Interface (TN767)
Circuitry Common to All Port CPs
Eight port circuits are provided on most port circuit packs. Twenty-four circuit capability is provided
on the DS1 circuit pack. The Multibutton Electronic Telephone (MET) Line, Tie Trunk, and Auxiliary
Trunk Circuit Packs each contain four port circuits. The port circuits provide an interface between
terminals/trunks and the TDM bus. The number of port circuit packs required varies according to
customer requirements and equipment configuration. Each of the System 25 port circuit packs
contain a number of common elements (see Figure 3-6) as well as the unique port circuits. The
common elements are as follows:
l Bus Buffers
The bus buffers are the digital interface between the backplane TDM bus wires (system
bus) and the on-board circuitry (data bus). They also receive and distribute clock and frame
signals.
l On-Board Microprocessor With External RAM
The on-board processor does all low-level functions, such as scanning for changes and
relay operations. In general, it carries out commands received from the Common Control
and reports status changes to it. The external RAM stores control channel information and
port-related information.
l SAKI (Sanity and Control Interface)
The SAKI is the control interface between the Common Control that sends information via
the network control circuit down the TDM buses and the on-board circuitry controlled by the
on-board microprocessor. The SAKI receives control information (down-link messages) on
the first five time slots and, as requested by the on-board microprocessor, transmits control
information (up-link messages) on these same time slots. (Continued on Page 3-13.)
November 1995
3-9