Acer Extensa 610 Service Guide

							2-24Service Guide2.4ALI M7101 (Power Management Unit)
2.4.1Features
· Four operating states - ON, DOZE, SLEEP, APM
· Programmable DOZE and SLEEP timer
· Programmable EL timer for backlight control
· Two Programmable APM timers
· Two output pins depending on operating state, each pin is programmable and power
configurable
· Provides system activity and EL activity monitorings, includes
· Video
· Harddisk
· Floppy
· Serial port
· Parallel port
· Keyboard
· Six programmable I/O address groups activity monitor
· Two programmable memory address groups activity monitor
· Multiple external wake-up events from DOZE or SLEEP to ON states
· External Push button
· Cover open
· Modem Ring
· RTC alarm
· DRQ
· Two level battery warning monitors
· 24 General Purpose I/O pins.  Each pin can be programmed to become input or output
· 32 External expandable general purpose output signals
· 32 External expandable general purpose input signals
· LCD control
· Rundown monitor detect
· Suspend wake-up detect
· 100-pin PQFP package 
						

							Major Chips Description2-252.4.2Pin Diagram                                                                          Vss
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CBEJ2
VDD5
FRAMEJ
IRDYJ
TRDYJ
DEVSELJ
PAR
CBEJ1
SMIJ
Vss
AD15
AD14
AD13
AD12
AD11
AD101
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA3
GPIOA2
GPIOA1
GPIOA0
Vss
CLK32
SEL1
SEL0
VDD5
DISPLAY
CCFT
FPVEE
SPKCTL
SQWO
SLED
DRQ
CRT75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 ALi
M7101
Figure 2-7M7101  Pin Diagram 
						

							2-26Service Guide2.4.3Pin Description
Table 2-4M7101 Pin DescriptionsNameNo.TypeDescriptionPCI interface : (42)PCICLK89IPCI Clock.  This is the PCI Bus interface CLK input signal.  This
clock frequency should not be more than 33 Mhz.  It is used by
internal PCI interface.AD[31:0]91-98,2-
9, 20-
25, 27,
28, 30-
37I/OPCI Address and Data bus.  These lines are connected to PCI Bus’
AD[31:0].   These lines contain Address and Data bus information
for PCI transaction.CBEJ[3:0]99,10,
17,29IPCI Bus Command and Byte enable.  These are PCI bus
commands at address phase and byte enable signals at data phase.
Since M7101 is PCI slave only, it will not drive CBEJ[3:0].  They are
inputs only.FRAMEJ12ICycle FRAME for PCI bus.  This signal indicates the beginning and
duration of a PCI access.DEVSELJ15ODevice select.  When M7101 has decoded the address as its own
cycle, it will assert DEVSELJ.IRDYJ13IInitiator Device Ready.  This signal indicates the initiator is ready to
complete the current data phase of transaction.TRDYJ14OTarget Device Ready.  This signal indicates that M7101 is ready to
complete the current data phase of transaction.PAR16OParity bit of PCI bus.  It is the even parity bit across AD[31:0] and
CBEJ[3:0]CLK & RESET interface : (3)CLK3262I32KHz clock.  This is 32KHz clock input, used by internal timers and
relative PMU circuit.PWGD40IPOWER GOOD.  When PWGD low means the VDD5&VDD3 power
supply is turned off.  When high, it means the power is available and
stable.  This signal will be sent to suspend circuit to disable the
suspend protected circuit when PWGD is high.  It will also be sent to
reset the circuit supplied by VDD5&VDD3 power.SUSRSTJ39ISUSPEND RESET.  SUSPEND circuit RESET signal.  When low,
the suspend circuit will be reset.  The suspend circuit is supplied by
the VDDS power.PMU Input event interface : (11)ACPWR49IAC power.  When plugged in or out, the AC adapter status will be
reflected at this signal.  Both low to high or high to low transition will
generate SMIJ.  An internal debounce is built-in to avoid the input
bouncing problem.  Both rising & falling will be detected.  This is a
smith-trigger input signal. 
						

							Major Chips Description2-27Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU Input event interface : (11)LBJ47ILow Battery.  First stage battery low indication. If low is detected
and Low Battery Timer is timeout, then battery low 1 SMIJ will be
generated every programmed interval time until battery low 2 SMIJ
is asserted or LB timer is reset. No debounce circuit is built in. Only
low level is detected.LLBJ48ILow Low Battery.  Second stage battery low indication.  If low is
detected and Low Low Battery Timer is timeout, then battery low 2
SMIJ will be generated every programmed interval time until both
LB and LLB timer are reset. No debounce circuit is built in. Only low
level is detected.
LLBJ  LBJ
 H     H     Normal condition
 H     L      Low Battery SMIJ will generate every interval.
                Low Low Battery SMIJ will not happen.
 L     X      Low Battery SMIJ will not happen.
                Low Low Battery SMIJ will generate every interval.COVSW
/SUSTAT241I/OCover switch (when 0F8h, D7=1).  Cover switch status input.  When
COVER is closed, the cover switch is also pressed and a COVSW
SMIJ will be generated.  When COVER is opened, the cover switch
will be released, a COVSW SMIJ will be generated, too.  Moreover,
both close and open will generate a doze-to-on or sleep-to-on SMIJ
to wake the system up if the system is in Doze or Sleep state,
respectively.  Debounce circuit is built in.  It detects both rising and
falling edge.
Suspend status 2 (when 0F8h, D7=0, it is default value).  It is
suspend status 2 signal during 0/5V suspend system.  It will be low
in normal.  When writing to port 0FAh, it will go high to close the
charger.  Any event of RI, RTC or HOTKEYJ will wake it up, and let
this pin go low again.RI42IModem Ring.  Modem ring input. A programmable ring counter will
count the ring pulse.  If the ring pulse reaches the counter‘s setting
value, a doze-to-on SMIJ or sleep-to-on SMIJ will be generated to
wakeup the system. If the system is already at on state, there will be
no new event or action. No debounce circuit is built in.  It only
detects rising edge.RTC43IRTC Alarm wakeup.  A low to high transition of this signal will
generate a doze-to-on or sleep-to-on SMIJ to wakeup the system.  If
the system is already at on state, there will be no new event or
action.  No debounce circuit is built in.   It only detects rising edge.DRQ52IFloppy DMA Request.  A low to high transition of this signal will
generate a doze-to-on or sleep-to-on SMIJ to wakeup the system. If
the system is at on state already, there will be no new event or
action. No debounce circuit is built in. It only detects rising edge. 
						

							2-28Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU Input event interface : (11)PS250IExternal PS2 MOUSE.  This signal represents whether the PS2
MOUSE is plugged in or not.  When a PS2 MOUSE is plugged in, a
high to low transition will generate a SMIJ.  When a PS2 MOUSE is
pulled out, a low to high transition will generate a SMIJ as well.  In
addition, the signal status can be read from BEEPER offset 0CBh
D1 register.  Debounce circuit is built in.  It detects both rising and
falling edges. This is a Smith-trigger input signal.CRT51IExternal CRT connector.  This signal represents whether the
External CRT connector is plugged in or not.  When an external
CRT connector is plugged in, a high to low transition will generate
an SMIJ.  When an external CRT connector is pulled out, a low to
high transition will generate an SMIJ, too. Moreover, the signal
status can be read from BEEPER offset 0CBh D0 register.
Debounce circuit is built in.  It  detects both rising and falling edges.
Smith-trigger input.HOTKEYJ44IHotKey press.  When HotKey is pressed, a high to low transition will
generate an SMIJ.  Debounce circuit is built in.  It detects only
falling edge.  This is a Smith-trigger input signal.FPVEE56ILCD backlight VEE.  LCD backlight VEE on/off control signal.
Internal circuit uses this signal to generate DISPLAY and CCFT
signals.  On one hand, if FPVEE goes from low to high, DISPLAY
will go high after 62.5ms to 125ms. If FPVEE goes low, DISPLAY
will go low immediately. On the other hand, FPVEE will AND with
offset 0D2h D0 to generate CCFT.  That is, if both FPVEE and offset
0D2h D0 are high then CCFT will be high or 1Khz clock with
programmable duty cycle.  Otherwise CCFT will be low.PMU output interface (9)SLED53OSquare LED display.  1Hz/2Hz square wave output.  It can drive the
LED to Flash.  When disabled, this signal will be kept at high/low
level as programmed.SPKCTL55OSpeaker output.  This signal is connected to speaker circuit to
generate sound directly.SQWO54OSquare wave output.  Square wave output with 1Hz or 2Hz.  When
disabled, this signal will keep at high/low level as programmed.SEL[1:0]61-60I/OProgrammable output control.  These two pins are programmable
output control pins at different state.  When Power on, these two
pins will be inputs and the Pull high( internal chip default is pull high
50K) or pull low (The pull low should use 4.7K resistor), will latch to
ON state register.  The values of ON, DOZE and SLEEP registers
corresponding to four operation status can be programmed.  That is,
when system is at different states, the corresponding  register value
will be sent to SEL[1:0]. 
						

							Major Chips Description2-29Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU output interface (9)CCFT57OBacklight control.  This signal is used to turn on/off LCD backlight.
FPVEE will AND with offset 0D2h D0 to generate CCFT.  That is, if
both FPVEE and offset 0D2h D0 are high then CCFT will be high or
1Khz signal with programmed duty cycle by offset 0Fbh D[4:0].
Otherwise CCFT will be low.DISPLAY58OLCD Display On/Off control.  This signal is used to control the LCD
display ON/OFF.  If FPVEE goes from low to high, DISPLAY will
also go high after a period of about 62.5ms to 125ms.  If not active,
it will go low immediately.SMIJ18OSystem Management Interrupt.  System Management interrupt
output. It is the SMIJ output when internal SMIJ is generated or the
IN_SMIJ input of the APM function is asserted.  The high/low active
level can be selected. There are three types of active method :
1. If offset 0D2h D7=1,D3=0, this signal will be asserted until
reading/writing all of SMIJ status register‘s bits. This can be treated
as a level SMIJ.
2. If offset 0D2h D7=0, D3=1, this signal will be asserted until
reading/writing all of SMIJ status register‘s bits or a programmed
interval time out.
3. If offset 0D2h D7=0, D3=0, this signal will be asserted for an
interval time. This can be treated as a pulse SMIJ.SUSTATE45OSUSPEND STATE.  When writing to port 0FAh or POSSTA goes
high, the SUSTATE will go high.  The system will enter SUSPEND
mode.  Only VDDS will supply the power, other VDD5 or VDD3 will
have no power. Only RI, RTC, HOTKEYJ or COVSW can wake up
the system and let the SUSTATE be low again.  The VDD5 and
VDD3 will supply power.General purpose I/O interface(24)General purpose I/O group AGPIOA[7:0]71-64I/OGeneral Purpose I/O group A.  These signals can be programmed to
be inputs or outputs.  Offset 0D9h D[7:0] control the I/O attributes.
When programmed to be outputs, offset 0D8h D[7:0] will be set to
corresponding signal.  When programmed to be inputs, the signal
can be read from the Offset 0D8h D[7:0] corresponding bits.
Offset 0D9h
  D[n] = 0     GPIOA[n]= Input
           GPIOA[n] value can be read from Offset 0D8h D[n]
            1     GPIOA[n]= Output
        Offset 0D8h D[n] value will be sent to GPIOA[n]  where n is
from 7 to 0GPIOA7
/POSSTA(71)IPositive input.  When offset 0F6h D13=‘1’, this pin will sense a high
level to active SUSTATE pin and force M7101 input suspend mode. 
						

							2-30Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group AGPIOA6
/SPEKIN(70)ISpeak input.  When offset 0F6h D6=‘1’, this pin will be speaker
input. The input signal will xor with SPKCTL internally.GPIOA5
/GPIOWB(69)OExternal General Purpose I/O B write.  When SQWO is pull low
4.7K, the GPIOA5 will become GPIOWA.  External General purpose
A R/W control pulse,  When write index 0F0h with a byte or a word.
A 74373 latch pulse will be generated at this pin.  The 74373 input
should be connected to PCI AD[23:16] if a byte command.  If a word
command, two 74373s will be used and inputs are connected to PCI
AD[31:16].  The write action also will write into the internal register.
So when reading the offset, the value will be sent by M7101 to host.GPIOA4
/GPIORBJ(68)OExternal General Purpose I/O B read.  When SQWO is pull low
4.7K, the GPIOA0 will become GPIORAJ.  External General
purpose A Read control pulse.  When Read index 0F1h with a byte
or a word, a 74245 OEJ pulse will be generated at this pin.  The
74245 output should be connected to PCI AD[23:16] if a byte
command.  If a word command, two 74245 will be used and4
outputs are connected to PCI AD[31:16].  When read index 0E1h,
M7101 will send DEVSELJ, TRDYJ but float the AD[31:0] because
the data will be sent by 74245.  The write action has no meaning
and nothing will be done.GPIOA3
/CONTRAST2
/SLOWDOW
N(67)O
/OContrast2.  When offset 0F6h D14=‘0’ and D9=‘1’, this pin will be
the LCD contrast output 2.  It is a 1Khz signal with programmable
duty cycle controlled by offset 0FBh D[15:13].
SLOWDOWN (default).  When offset 0F6h D14=‘1’, this pin will be
the slow down clock control output pin.GPIOA2
/CONTRAST1(66)OContrast1.  When offset 0F6h D14=’0’ and D8=’1’, this pin will be
the LCD contrast output1.  It is a 1 KHz signal with programmable
duty cycle controlled by offset 0FBh D[12:8].GPIOA1
/GPIOWA(65)OExternal General Purpose I/O A write.  When SPKCTL is pull low
4.7K, the GPIOA1 will become GPIOWA.  External General purpose
A R/W control pulse,  When write index 0E0h with a byte or a word.
A 74373 latch pulse will be generated at this pin, The 74373 input
should be connected to PCI AD[23:16] if a byte command. If a word
command , two 74373s will be used and inputs are connected to
PCI AD[31:16]. The write action also will write into the internal
register.  So when reading the offset, the value will be sent by
M7101 to host. 
						

							Major Chips Description2-31Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group AGPIOA0
/GPIORAJ(64)OExternal General Purpose I/O A read.  When SPKCTL is pull low
4.7K, the GPIOA0 will become GPIORAJ.  External General
purpose A Read control pulse,  When Read index 0E1h with a byte
or a word.  A 74245 OEJ pulse will be generated at this pin.  The
74245 output should be connected to PCI AD[23:16] if a byte
command.  If a word command, two 74245s will be used and
outputs are connected to PCI AD[31:16].  When read index 0E1h,
M7101 will send DEVSELJ, TRDYJ but float the AD[31:0] because
the data will be sent by 74245.  The write action has no meaning
and nothing will be done.General purpose I/O interface(24)General purpose I/O group BGPIOB[7 :0]88,85,
87,86,
84-81I/OGeneral Purpose I/O group B.  These signals can be programmed to
be input or output. Offset 0DBh D[7:0] control the I/O attribute.
When programmed to be output, Offset 0DAh D[7:0] will set to
corresponding signal.  When programmed to be input, the signal
can be read from the Offset 0DAh D[7:0] corresponding bits.
Offset 0DBh
    D[n] = 0 : GPIOB[n]=input
             GPIOB[n] value can be read from Offset 0DAh D[n]
               1 : GPIOB[n]=Output
              Offset 0DAh D[n] value will send to GPIOB[n]
                        n value is from 7 to 0GPIOB7
/STPCLKJ(88)OStop clock signal.  When DISPLAY is pulled low or offset 0F6h
D14=‘1’, this pin will become stop clock signal output.  It may be
connected to CPU to force it into STPGNT or STPCLK mode.  Write
port 0EFh will assert this function.GPIOB6
/AMSTATJ(85)OAPM State. When DISPLAY is pulled low, this pin will be APM state.
It may be connected to clock generator to slow down clock.  It is
asserted when HALT or STPGNT cycle is detected and recovers
when IN_SMIJ, IN_INTR or IN_INIT is asserted.  System can use
this signal to know the APM status, and slow down the speed or turn
off some peripheral power to decrease the power consumption.
This signal will be synchronized with PCICLK‘s rising or falling edge.GPIOB5
/OUT_INIT(87)OINIT Output.  When DISPLAY is pulled low, this pin will be INIT
output. It will be disabled when IN_INIT is detected and AMSTATJ is
asserted.  Then, it will be sent as a 16 PCICLK wide pulse after
AMSTATJ is deasserted.  Otherwise, it will be the same with
IN_INIT. It may be connected to CPU.GPIOB4
/OUT_INTR(86)OINTR Output.  When DISPLAY is pulled low, this pin will become
INTR output. It may be connected to CPU.  When AMSTATJ is
asserted, IN_INTR will be masked until AMSTATJ is de-asserted. 
						

							2-32Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group BGPIOB3
/IN_BRDYJ(84)IBRDYJ Input.  When DISPLAY is pulled low, this pin will be BRDYJ
input. It must be connected to CPU.GPIOB2
/IN_INIT(83)IINIT Input.  When DISPLAY is pulled low, this pin will be INIT input.GPIOB1
/IN_SMIJ(82)ISMIJ Input.  When DISPLAY is pulled low, this pin will be SMIJ
input.GPIOB0
/IN_INTR(81)ISMIJ Input.  When DISPLAY is pulled low, this pin will be INTR
input.General purpose I/O interface(24)General purpose I/O group CGPIOC[7:0]80-77,
75-72I/OGeneral Purpose I/O group C.  When these signals are set to
GPIOC[7:0], these signals can be programmed to be input or
output.  Offset 0DDh D[7:0] control the I/O attribute.  When
programmed to be output, offset 0DCh D[7:0] will set to
corresponding signal.  When programmed to be input, the signal
can be read from the Offset 0DCh D[7:0] corresponding bits.
Offset 0DDh
   D[n] = 0 : GPIOC[n]=input
            GPIOC[n] value can be read from Offset 0DCh D[n]
             1 : GPIOC[n]=Output
             Offset 0DAh D[n] value will send to GPIOC[n]
                        n value is from 7 to 0GPIOC7
/VCSJ(80)IVGA Chip select.  When offset 0F6h D12=0, this signal is GPIOC7.
When D12=1, this signal will become VCSJ.
When access to VGA memory range, VGA chip will set this signal to
active low. The internal circuit use this signal to monitor the VGA
active to restart the timer or generate SMIJ. No debounce is built in.
Low level detect.GPIOC6
/SETUPJ(79)ISetup switch.  When offset 0F6h D11=0, this signal is GPIOC6.
When D11=1, this signal will become SETUPJ.
Setup switch input. A transition will generate setup switch SMIJ.
Debounce circuit is built in. Both rising and falling edges are
detected. Smith-trigger input. 
						

							Major Chips Description2-33Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group CGPIOC5
/EXTSW(78)External suspend/resume switch.  When offset 0F6h D10=0, this
signal is  GPIOC5. When D10=1, this signal will become EXTSW.
External Suspend/Resume switch input. Pressing this switch will
generate SMIJ to suspend or resume the system. When the system
is at resume status(On, Doze), pressing this switch will enter
Suspend status(Sleep). When the system is at Suspend
status(Sleep), pressing the switch will enter ON status. Debounce
circuit is built in. Both rising and falling edge are detected. Smith-
trigger input.GPIOC[4]
/EJECT(77)External Eject SMIJ trigger. 1.  When index 0F6h D7=0, this signal
is GPIOC(4).  When it is 1,  this signal will become EJECT
When a rising/falling edge happens at this input, an SMIJ will be
generated. Built in debounce circuit.GPIOC[3]
/DOCKJ(75)Docking insert detected. When index 0F6h D7=0, this signal is
GPIOC[3].  When it is 1, this signal will become DOCKJ
When a rising/falling edge happens at this input, an SMIJ will be
generated. Built in debounce circuit.GPIOC[2]
/BIOSA17(74)BIOS address ROM A17
When CCFT is low, this signal will become BIOSA17.GPIOC[1]
/BIOSA16(73)BIOS address ROM A16
When CCFT is low, this signal will become BIOSA16.GPIOC[0]
/ISA16(72)ISA SLOT address A16
When CCFT is pulled low, this signal will become ISA16.
These two signals connect BIOS ROM A17 & A16 to distinguish
the four parts of BIOS ROM and decided by offset 0D2h D[2:1].
 D2   D1   ISA16     BIOSA17  BIOSA16     ROM region
  X     X      1                    0          1               1
  X     0      0                    0           0              0
  0     1      0                     1           0              2
  1     1      0                     1           1              3
We divided the 256K byte ROM into four parts. E region will
occupy three parts--0,2,3,  F region will occupy one part--1.  So,
when CPU accesses to F region, that is, ISA16=1, then system will
access ROM region 1, F segment. The E region has three parts
overlaying the same address, software can use offset 0D2h D[2:1]
to choose which ROM region to be accessed.