Acer Extensa 610 Service Guide

							2-74Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)     TERMINALNAME         NOI /OTYPEFUNCTIONInterrupt TerminalsIRQ15/
RI_OUT            163I/OInterrupt Request 15. This terminal indicates an interrupt request
from one of the PC Cards. RI_OUT allows the RI input from the 1 6-
bit PC Card, CSTSCHG from CardBus Cards or PC Card removal
events to be output to the system. This signal is configured in the
Card Control Register of the TI Extension Registers.PC Card Power Switch TerminalsLATCH    150OPower Switch Latch is asserted by the PCI1131 to indicate to the PC
Card power switch that the data on the DATA line is valid.CLOCK     151OPower Switch Clock. Information on the DATA line is sampled at the
rising edge of CLOCK. The frequency of the clock is derived from
dividing the PCICLK by 36. The maximum frequency of this signal is
2 MHz.DATA     152OPower Switch Data is used by the PCI1131 to serially communicate
socket power control information.Speaker Control TerminalSPKROUT/
SUSPEND    149I/OSpeaker. SPKROUT carries the digital audio signal from the PC
Card.
SUSPEND, when enabled, this signal places the PCI1131 in
PCI1131 Suspend Mode (Section 6.0) . This pin is configured in the
Card Control Register (Section 7.29) of the TI Extension Registers.Power Supply TerminalsGND
13,22,44 75 96,129,
153, 167, 81
194,207IDevice ground terminalsVccA120IPower-supply terminal for PC Card A (5V or 3.3V)VccB38IPower-supply terminal for PC Card B (5V or 3.3 V)VccP148, 172IPower-supply terminal for PCI interface (5V or 3.3V)Vcc
7, 31, 64, 86, 113,
143,164, 175, 187,
201IPower-Supply terminal for core logic (3.3V) 
						

							Major Chips Description2-752.7NS87336VJG Super I/O Controller
The PC87336VJG is a single chip solution for most commonly used I/O peripherals in ISA, and
EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs,
and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the
peripherals and a set of configuration registers are also implemented in this highly integrated
member of the Super l/O family. Advanced power management features, mixed voltage operation
and integrated Serial-lnfrared(both IrDA and Sharp) support makes the PC87336 an ideal choice
for low-power and/or portable personal computer applications.
The PC87336 FDC uses a high performance digital data separator eliminating the need for any
external filter components. It is fully compatible with the PC8477 and incorporates a superset of
DP8473, NEC PD765 and N82077 floppy disk controller functions. All popular 5.25” and 3.5”
floppy drives, including the 2.88 MB 3.5” floppy drive, are supported. In addition, automatic media
sense and 2 Mbps tape drive support are provided by the FDC.
The two UARTs are fully NS16450 and NS16550 compatible. Both ports support MIDI baud rates
and one port also supports IrDA’s the HP SIR and Sharp SIR compliant signaling protocol.
The parallel port is fully IEEE 1284 level 2 compatible. The SPP(Standard Parallel Port) is fully
compatible wit ISA and EISA parallel ports. In addition to the SPP, EPP(Enhanced Parallel Port)
and ECP(Extended Capabilities Port) modes are supported by the parallel port.
A set of configuration registers are provided to control the Plug and Play and other various
functions of the PC87336. These registers are accessed using two 8-bit wide index and data
registers. The ISA I/O address of the register pair can be relocated using a power-up strapping
option and the software configuration after power-up.
When idle, advanced power management features allows the PC87336 to enter extremely low
power modes under software control. The PC87336 can operate from a 5V or a 3.3V power
supply. An unique I/O cell structure allows the PC87336 to interface directly with 5V external
components while operating from a 3.3V power supply.
2.7.1Features
· 100% compatible with ISA, and EISA architectures
· The Floppy Disk Controller:
· Software compatible with the DP8473, the 765A and the N82077
· 16-byte FlFO(disabled by default)
· Burst and Non-Burst modes
· Perpendicular Recording drive support
· New high-performance internal digital data separator(no external filter components
required)
· Low-power CMOS with enhanced power-down mode
· Automatic media-sense support, with full IBM TDR(Tape Drive Register) implementation
· Supports fast 2 Mbps and standard 1 Mbps/500 kbps/250 kbps tape drives 
						

							2-76Service Guide· The Bidirectional Parallel Port:
· Enhanced Parallel Port(EPP) compatible
· Extended Capabilities Port(ECP) compatible, including level 2 support
· Bidirectional under either software or hardware control
· Compatible with ISA, and EISA, architectures
· Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy
Disk Drive(FDD)
· Includes protection circuit to prevent damage to the parallel port when a connected
printer is powered up or is operated at a higher voltage
· The UARTs:
· Software compatible with the PC16550A and PC16450
· MIDI baud rate support
· Infrared support on UART2(IrDA and Sharp-compliant)
· The Address Decoder
· 6 bit or 10 bit decoding
· External Chip Select capability when 10 bit decoding
· Full relocation capability(No limitation)
· Enhanced Power Management
· Special configuration registers for power-down
· Enhanced programmable power-down FDC command
· Auto power-down and wake-up modes
· 2 special pins for power management
· Typical current consumption during power-down is less than 10 uA
· Reduced pin leakage current
· Mixed Voltage support
· Supports standard 5V operation
· Supports 3.3V operation
· Supports mixed internal 3.3V operation with 3.3V/5V external configuration
· The General Purpose Pins:
· 2 pins, for 2 separate programmable chip select decoders, can be programmed for game
port control 
						

							Major Chips Description2-77· Plug and Play Compatible:
· 16 bit addressing(full programmable)
· 10 selectable IRQs
· 3 selectable DMA Channels
· 3 SIRQ Inputs allows external devices to mapping IRQs
· 100-Pin TQFP package - PC87336VJG
2.7.2Block DiagramConfiguration
RegistersUART
(16550 or 16450)UART
+ IrDA/HP & Sharp IR
(16550 or 16450)General
Purpose
RegistersPower
Down LogicIEEEE1284
Parallel PortHifh Current DriverFloppy Disk
Controller with
Digital Data
Separator
(Enhabced 8477)I/O PortsControl
InterruptDataHandshakeFloppy
Drive
Interface
OSCInterrupt
and
DMAFloppy
Drive
Interface InterruptIR
Interface Serial
Interface Interrupt Serial
Interface Config.
Inputs
Figure 2-15NS87336VJG Block Diagram 
						

							2-78Service Guide2.7.3Pin DiagramFigure 2-16NS87336VJG Pin Diagram 
						

							Major Chips Description2-792.7.4Pin Description
Table 2-14NS87336VJG Pin DescriptionsPinNo.I/ODescriptionA15-A067, 64,
62-60,
29, 19-
28IAddress.  These address lines from the microprocessor determine which
internal register is accessed.  A0-A15 are dont cares during DMA
transfer./ACK83IParallel Port Acknowledge.  This input is pulsed low by the printer to
indicate that it has received the data from the parallel port.  This pin has
a nominal 25 KW pull-up resistor attached to it.ADRATE0,
ADRATE196,
46OFDD Additional Data Rate 0,1.  These outputs are similar to DRATE0, 1.
They are provided in addition to DRATE0, 1.  They reflect the currently
selected FDC data rate, (bits 0 and 1 in the Configuration Control
Register (CCR) or the Data Rate Select Register (DSR), whichever was
written to last).  ADRATE0 is configured when bit 0 of ASC is 1.
ADRATE1 is configured when bit 4 of ASC is 1.  (See IRQ5 and
DENSEL for further information)./AFD76I/OParallel Port Automatic Feed XT.  When this signal is low, the printer
automatically line feed after printing each line.  This pin is in a tristate
condition 10 ns after a 0 is loaded into the corresponding Control
Register bit.  The system should pull this pin high using a 4.7 KW
resistor.AEN18IAddress Enable.  When this input is high, it disables function selection
via A15-A0.  Access during DMA transfer is not affected by this pin./ASTRB79OEPP Address Strobe.  This signal is used in EPP mode as address
strobe.  It is an active low signal.BADDR0,
BADDR172,
71IBase Address.  These bits determine one of the four base addresses
from which the Index and Data Registers are offset.   An internal pull-
down resistor of 30 KW is on this pin.  Use a 10 KW resistor to pull this
pin to VCC.BOUT1,
BOUT271,
63OUARTs Baud Output.  This multi-function pin supports the associated
serial channel Baud Rate generator output signal if the test mode is
selected in the Power and Test Configuration Register and the DLAB bit
(LCR7) is set.  After the Master Reset, this pin offers the SOUT function.BUSY82IParallel Port Busy.  This pin is set high by the printer when it cannot
accept another character.  It has a nominal 25 KW pull-down resistor
attached to it.CFG0
CFG163,
69IConfiguration on Power-up.  These CMOS inputs select 1 of 4 default
configurations in which the PC87336 powers up.  An internal pull-down
resistor of 30 KW is on each pin.  Use a 10 KW resistor to pull these pins
to VCC. 
						

							2-80Service GuideTable 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescription/CS0,
/CS151, 3OProgrammable Chip Select.  /CS0, 1 are programmable chip select
and/or latch enable and/or output enable signals that can be used as
game port, I/O expand, etc.  The decoded address and the assertion
conditions are configured via the 87336VJG’s configuration registers./CTS1,
/CTS272, 64IUARTs Clear to Send.  When low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal is a modem
status input.  The CPU tests the condition of this /CTS signal by
reading bit 4 (CTS) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 4 is the complement of the CTS
signal.  Bit 0 (DCTS) has no effect on the transmitter.
/CTS2 is multiplexed with A13.  When it is not selected, it is masked
to “0”.
NOTE: Whenever the MSR DCTS bit is set, an interrupt is generated
if Modem Status interrupts are enabled.D7-D010-17I/OData.  These are bidirectional data lines to the microprocessor.  D0 is
the LSB and D7 is the MSB.  These signals have a 24 mA (sink)
buffered outputs./DACK0
/DACK1
/DACK253,
52,
3IDMA Acknowledge 0, 1, 2.  These active low inputs acknowledge the
DMA request and enable the /RD and /WR inputs during a DMA
transfer. It can be used by one of the following: FDC or Parallel Port.
If none of them uses this input pin, it is ignored.  If the device which
uses on of this pins is disabled or configured with no DMA, this pin is
also ignored.
/DACK0, 1, 2should be held high during I/O accesses./DCD1, /DCD275, 67IUARTs Data Carrier Detect.  When low, this indicates that the
modem or data set has detected the data carrier.  The /DCD signal is
a modem status input.  The CPU tests the condition of this /DCD
signal by reading bit 7 (DCD) of the Modem Status Register (MSR)
for the appropriate serial channel.  Bit 7 is the complement of the
DCD signal.  Bit 3 (DDCD) of the MSR indicates whether DCD input
has changed state since the previous reading of the MSR.
NOTE: Whenever the MSR DDCD bit is set, an interrupt is generated
if Modem Status interrupts are enabled. 
						

							Major Chips Description2-81Table 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescriptionDENSEL
(Normal Mode)46OFDC Density Select.  DENSEL indicates that a high FDC density data
rate (500 Kbs, 1 Mbs or 2 Mbs) or a low density data rate (250 or 300
Kbs) is selected.  DENSEL is active high for high density (5.25-inch
drives) when IDENT is high, and active low for high density (3.5-inch
drives) when IDENT is low.  DENSEL is also programmable via the
Mode command.DENSEL
(PPM Mode)76OFDC Density Select.  This pin offers an additional Density Select
signal in PPM Mode when PNF=0./DIR
(Normal Mode)39OFDC Direction.  This output determines the direction of the floppy disk
drive (FDD) head movement (active = step-in; inactive = step-out)
during a seek operation.  During reads or writes, DIR is inactive./DIR
(PPM Mode)78OFDC Direction.  This pin offers an additional Direction signal in PPM
Mode when PNF = 0./DR0,
/DR1
(Normal Mode)42, 43OFDC Drive Select 0, 1.  These are the decoded drive select outputs
that are controlled by Digital Output Register bits D0, D1.  The Drive
Select outputs are gated with DOR bits 4-7.  These are active low
outputs.  They are encoded with information to control four FDDs
when bit 4 of the Function Enable Register (FER) is set.  DR0
exchanges logical drive values with DR1 when bit 4 of Function
Control Register is set./DR1
(PPM Mode)83OFDC Drive Select 1.  This pin offers an additional Drive Select signal
in PPM Mode when PNF = 0.  It is drive select 1 when bit 4 of FCR is
0.  It is drive select 0 when bit 4 of FCR is 1.  This signal is active
low./DR2347OFDC Drive 2 or 3.  /DR23 is asserted when either Drive 2 or Drive 3 is
assessed(except during logical drive exchange)./DRATE0
/DRATE1
(Normal Mode)50, 49OFDC Data Rate 0, 1.  These outputs reflect the currently selected
FDC data rate (bits 0 and 1 in the Configuration Control Register
(CCR) or the Data Rate Select Register (DSR), whichever was written
to last).  The pins are totem-pole buffered outputs (6 mA sink, 6 mA
source)./DRATE0
(PPM Mode)85OFDC Data Rate 0.  This pin provides an additional Data Rate signal,
in PPM mode, When PNF=0.DRQ0
DRQ1
DRQ254
31
2ODMA Request 0, 1, 2.   \An active high output that signals the DMA
controller that a data transfer is required.  This DMA request can be
sourced by one of the following: FDC or Parallel Port.
When it is not sourced by and of them, it is in TRI-STATE.  When
the sourced device is disabled or when the sourced device is
configured with no DMA, it is also in TRI-STATE.  Upon reset, DRQ2
is used by the FDC. 
						

							2-82Service GuideTable 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescription/DRV247IFDD Drive2.  This input indicates whether a second disk drive has
been installed.  The state of this pin is available from Status Register
A in PS/2 mode.  (See PNF for further information)./DSKCHG
(Normal Mode)30IDisk Change.  The input indicates if the drive door has been opened.
The state of this pin is available from the Digital Input Register.  This
pin can also be configured as the RGATE data separator diagnostic
input via the Mode command./DSKCHG
(PPM Mode)87IDisk Change.  This pin offers an additional Disk Change signal in
PPM Mode when PNF = 0./DSR1
/DSR274, 66IUARTs Data Set Ready.  When low, this indicates that the data set or
modem is ready to establish a communications link.  The DSR signal
is a modem status input.  The CPU tests the /DSR signal by reading
bit 5 (DSR) of the Modem Status Register (MSR) for the appropriate
channel.  Bit 5 is the complement of the DSR signal.  Bit 1 (DDSR) of
the MSR indicates whether the DSR input has changed state since
the previous reading of the MSR.
NOTE:  Whenever the DDSR bit of the NSR is set, an interrupt is
generated if Modem Status interrupts are enabled./DSTRB76OEPP Data Strobe.  This signal is used in EPP mode as data strobe.
It is an active low signal./DTR1
/DTR269, 61OUARTs Data Terminal Ready.  When low, this output indicates to the
modem or data set that the UART is ready to establish a
communications link.  The DTR signal can be set to an active low by
programming bit 0 (DTR) of the Modem Control Register to a high
level.  A Master Reset operation sets this signal to its inactive (high)
state.  Loop mode operation holds this signal to its inactive state./ERR77IParallel Port Error.  This input is set low by the printer when an error
is detected.  This pin has a nominal 25 KOHM pull-up resistor
attached to it./HDSEL
(Normal Mode)32OFDC Head Select.  This output determines which side of the FDD is
accessed.  Active selects side 1, inactive selects side 0./HDSEL
(PPM Mode)77OFDC Head Select.  This pin offers an additional Head Select signal in
PPM Mode when PNF = 0.IDLE41OFDD IDLE.  IDLE indicates that the FDC is in the IDLE state and can
be powered down.  Whenever the FDC is in IDLE state, or in power-
down state, the pin is active high./INDEX45IIndex.  This input signals the beginning of a FDD track./INDEX
(Normal Mode)92IIndex.  This pin gives an additional Index signal in PPM mode when
PNF = 0./INIT
(PPM Mode)78I/OInitialize.  When this signal is low, it causes the printer to be
initialized.  This pin is in a tristate condition 10 ns after a 1 is loaded
into the corresponding Control Register bit.  The system should pull
this pin high using a 4.7 KW resistor. 
						

							Major Chips Description2-83Table 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescriptionIORCHDY51OI/O Channel Ready.  When IORCHDY is driven low, the EPP extends
the host cycle.IRQ3, 4
IRQ5-7
IRQ9-11
IRQ12, 15
(PnP Mode)99, 98
96-94,
55-57,
66, 58I/OInterrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15.  This pin can be a totem-
pole output or an open-drain output.  The interrupt can be sourced by
one of the following: UART1 and/or UART2, parallel port, FDC,
SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.
IRQ5 is multiplexed with ADRATE0.
IRQ12 is multiplexed with /DSR2 and IRRX2.
IRQ15 is multiplexed with SIRQI1.IRQ3, 4
(Legacy Mode)99, 98OInterrupt 3 and 4.  These are active high interrupts associated with
the serial ports.  IRQ3 presents the signal if the serial channel ahs
been designated as COM2 or COM4.  IRQ4 presents the signal if the
serial port is designated as COM1 or COM3.  The interrupt is reset
low (inactive ) after the appropriate interrupt service routine is
executed.IRQ5
(Legacy Mode)96I/OInterrupt 5.  Active high output that indicates a parallel port interrupt.
When enabled, this pin follows the /ACK signal input.  When it is noe
enabled, this signal is tri-state.  This pin ia I/O only when ECP is
enabled, and IRQ5 is configured.IRQ6
(Legacy Mode)95OInterrupt 6.  Active high output to signal the completion of the
execution phase for certain FDC commands.  Also used to signal
when a data transfer is ready during a non-DMA operation.IRQ7
(Legacy Mode)94I/OInterrupt 7.  Active high output that indicates a parallel port interrupt.
When enabled, this signal follows the /ACK signal intput.  When it is
not enabled, this signal is tri-state.  This pin is I/O only when ECP is
enabled, and IRQ7 is configured.IRRX1
IRRX265, 66IIrDA or SHARP- Infrared Receive.  One of these pins is the infrared
serial data input.
IRRX1 is multiplexed with SIN2.
IRRX2 is multiplexed with /DSR2 and IRQ12.IRTX63OInfrared Transmit. Infrared serial data output.  Software configuration
selects either IrDA or Sharp-IR protocol.
This pin is multiplexed with SOUT2/BOUT/CFG0.MR100IMaster Reset.  Active high output that resets the controller to the idle
state and resets all disk interface outputs to their inactive states.  The
DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values.  The
Specify command parameters are not affected