Acer Extensa 610 Service Guide

							2-34Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPower PinsVDD5 x 311,59,76P5V VDD inputVDD3 x 226,100P3.3V VDD inputVDDS x 146P5V Suspend VDD input.   This pin supplies to RI, RTC, HOTKEYJ,
COVSW, SUSTATE, PWGD, SUSRSTJ pad.VSS x 51,19,38,
63,90PVSS Ground.2.4.4Different Pin definition setting
· SLED, CCFT, DISPLAY, SPKCTL, SQWO and GPIOC2 pins are all internal pull high 50K
ohms.  The blank part of following table means keeping the original pin definition.
· When SLED default is pulled high, the chip will be in normal mode.
· When SLED is pulled low by 4.7K resistor, the chip will be in test mode.
· When GPIOC2 pull low, the PCI ports are 0078/007A and offset 0F6h D15 will be set, otherwise,
0178/017A.
Table 2-5M7101 Different Pin Definition SettingOriginal pindefinitionCCFTpull low 4.7KDISPLAYpull low 4.7KSPKCTLpull low 4.7KSQWOpull low 4.7Koffset 0F6h D1=1offset 0F6h D2=1offset 0F6h D3=1offset 0F6h D4=1GPIOA5GPIOWBGPIOA4GPIORBJGPIOA1GPIOWAGPIOA0GPIORAJGPIOB7STPCLKJGPIOB6AMSTATJGPIOB5OUT_INITGPIOB4OUT_INTRGPIOB3IN_BRDYJGPIOB2IN_INITGPIOB1IN_SMIJGPIOB0IN_INTRGPIOC2BIOSA17GPIOC1BIOSA16GPIOC0ISA16 
						

							Major Chips Description2-35When offset 0F6h, D5=1 and offset 0FBh, D7=1; GPIOB[7:0] and GPIOA[7:0] output some clocks
for testing.  The clocks are OTCOUNT, O16K, TCLK2, TCLK3, O128HZ, O16HZ, O8HZ, O4HZ,
O2HZ, O1Hz, ELCOUNT, DZCOUNT, SLCOUNT, RICOUNT, LBCOUNT[1:0].
Table 2-6M7101 Original Pin Definition SettingOriginalpindefinitionD6=1D7=1D8=1D9=1D10=1D11=1D12=1D13=1D14=1GPIOA7POSSTAGPIOA6SPEKINGPIOA3CONTRAST2SLOWDNGPIOA2CONTRAST1GPIOB7STPCLKJGPIOB3BRDYJGPIOC7VCSJGPIOC6SETUPGPIOC5EXTSWGPIOC4EJECYJGPIOC3DOCKJFollowing is the default pulled values of GPIOA, GPIOB and GPIOC :
· Pull high : GPIOA0, GPIOA4, GPIOB1, GPIOB3, GPIOB6, GPIOB7, GPIOC1, GPIOC2,
GPIOC5, GPIOC6, GPIOC7.
· Pull low : Other GPIO pins. 
						

							2-36Service Guide2.4.5Numerical Pin List
Table 2-7M7101 Numerical Pin ListNo.Pin NameTypeNo.Pin NameType1VSSP51CRTI2AD23I/O52DRQI3AD22I/O53SLEDO4AD21I/O54SQWOO5AD20I/O55SPKCTLO6AD19I/O56FPVEEI7AD18I/O57CCFTO8AD17I/O58DISPLAYO9AD16I/O59VDD5P10CBEJ2I60SEL0I/O11VDD5P61SEL1I/O12FRAMEJI62CLK32I13IRDYJI63VSSP14TRDYJO64GPIOA0I/O15DEVSELJO65GPIOA1I/O16PARO66GPIOA2I/O17CBEJ1I67GPIOA3I/O18SMIJO68GPIOA4I/O19VSSP69GPIOA5I/O20AD15I/O70GPIOA6I/O21AD14I/O71GPIOA7I/O22AD13I/O72GPIOC0I/O23AD12I/O73GPIOC1I/O24AD11I/O74GPIOC2I/O25AD10I/O75GPIOC3I/O26VDD3P76VDD5P27AD9I/O77GPIOC4I/O28AD8I/O78GPIOC5I/O29CBEJ0I79GPIOC6I/O30AD7I/O80GPIOC7I/O31AD6I/O81GPIOB0I/O32AD5I/O82GPIOB1I/O33AD4I/O83GPIOB2I/O34AD3I/O84GPIOB3I/O35AD2I/O85GPIOB6I/O36AD1I/O86GPIOB4I/O37AD0I/O87GPIOB5I/O38VSSP88GPIOB7I/O39SUSRSTJI89PCICLKI40PWGDI90VSSP41COVSWI/O91AD31I/O42RII92AD30I/O43RTCI93AD29I/O44HOTKEYJI94AD28I/O45SUSTATEO95AD27I/O46VDDSP96AD26I/O47LBJI97AD25I/O48LLBJI98AD24I/O49ACPWRI99CBEJ3I50PS2I100VDD3P 
						

							Major Chips Description2-372.4.6Alphabetical Pin List
Table 2-8M7101 Alphabetical Pin ListNo.Pin NameTypeNo.Pin NameType49ACPWRI68GPIOA4I/O37AD0I/O69GPIOA5I/O36AD1I/O70GPIOA6I/O35AD2I/O71GPIOA7I/O34AD3I/O81GPIOB0I/O33AD4I/O82GPIOB1I/O32AD5I/O83GPIOB2I/O31AD6I/O84GPIOB3I/O30AD7I/O85GPIOB6I/O28AD8I/O86GPIOB4I/O27AD9I/O87GPIOB5I/O25AD10I/O88GPIOB7I/O24AD11I/O72GPIOC0I/O23AD12I/O73GPIOC1I/O22AD13I/O74GPIOC2I/O21AD14I/O75GPIOC3I/O20AD15I/O77GPIOC4I/O9AD16I/O78GPIOC5I/O8AD17I/O79GPIOC6I/O7AD18I/O80GPIOC7I/O6AD19I/O44HOTKEYJI5AD20I/O13IRDYJI4AD21I/O47LBJI3AD22I/O48LLBJI2AD23I/O16PARO98AD24I/O89PCICLKI97AD25I/O50PS2I96AD26I/O40PWGDI95AD27I/O42RII94AD28I/O43RTCI93AD29I/O60SEL0I/O92AD30I/O61SEL1I/O91AD31I/O53SLEDO29CBEJ0I18SMIJO17CBEJ1I54SQWOO10CBEJ2I55SPKCTLO99CBEJ3I39SUSRSTJI57CCFTO45SUSTATEO62CLK32I14TRDYJO41COVSWI/O26VDD3P51CRTI100VDD3P15DEVSELJO59VDD5P58DISPLAYO11VDD5P52DRQI76VDD5P56FPVEEI46VDDSP12FRAMEJI1VSSP64GPIOA0I/O19VSSP65GPIOA1I/O38VSSP66GPIOA2I/O63VSSP67GPIOA3I/O90VSSP 
						

							2-38Service Guide2.4.7Function Description
The function blocks of M7101 are as follows :
1. PCI Interface
2. State Controller
3. Timer
4. Wake up event handler
5. Activity monitor
6. Battery monitor
7. General Purpose Input/Output (GPIO)
8. SMIJ Generator
9. SUSPEND monitor
10. APM monitor
11. Rundown Emulation
12. LCD control
13. SLOWDOWN control
PCI interface
The PCI interface is running at PCICLK frequency.  From the point of PCI bus, M7101 is a hidden
component.  There are no PCI configuration spaces built in.  So using PCI configuration read/write
method cannot detect the existence of M7101.
M7101 just decodes the I/O 0178h/017Ah or 0078h/007Ah address.  When it detects the address,
it will assert the DEVSELJ signal and TRDYJ when data is ready.  M7101 is only a PCI slave
device, no REQJ and GNTJ signal required.  All the PCI interface timing can meet the
requirements of PCI spec. V2.1.
M7101 will monitor the PCI bus behavior to detect the Device access like HDD, SIO, PIO, VGA
memory range, Floppy, KBC and IO&MEM group.  It will decode these addresses but not assert
DEVSELJ.  The interface is static design. So the input PCICLK can be changed from 33 MHz to 0
Hz without glitch.
There is a Lock register at offset 0D1h.  When set D5 to 1 will unlock I/O port 017Ah/007Ah.  Host
can read or write I/O port 017Ah/007Ah.  When set D5 to 0, then Host cannot I/O read/write I/O
port 017Ah/007Ah except the offset 0D1h.  No matter lock or unlock, when access to I/O port
017Ah, DEVSELJ will always be active. 
						

							Major Chips Description2-39Table 2-9M7101 PCI Interface Lock RegisterActionI/O Port0178h/0078hI/O Port 017Ah/007AhLock Readnot available
except offset
0D1hnot available except offset 0D1hLock Writenot available
except offset
0D1hnot available except offset 0D1hUnlock
ReadavailableavailableUnlock
WriteavailableavailableState Machine for PCI Interface.
FRAMEJ=1IDLEnocycle=1, when FRAMEJ=1 and IRDYJ=1.
             =0, when others.HIT=1, when read/write port 178-17B.
=0, when others.FRAMEJ=1
FRAMEJ=0
IRDYJ=0 IRDYJ=1HIT=0 nocycle=0 and
nocycle=0 and
HIT=1HIT=0 and
FRAMEJ=1nocycle=1 orFRAMEJ=0BUS_BUSYTURN_AROVER_SHITCMD3HITCMD2HITCMD1START_SFigure 2-8State Machine for PCI Interface 
						

							2-40Service Guide2.5   C&T 65550 High Performance Flat Panel/CRT VGA Controller
The C&T65550 of high performance multimedia flat panel / CRT GUI accelerators extend CHIPS’
offering of high performance flat panel controllers for full-featured note books and sub-notebooks.
The C&T65550 offers 64-bit high performance and new hardware multimedia support features.
2.5.1Features
HIGH PERFORMANCEBased on a totally new internal architecture, the C&T65550, integrates a powerful 64-bit graphics
accelerator engine for Bit Block Transfer (BitBLT), hardware cursor, and other functions intensively
used in graphical User Interfaces (GUls) such as Microsoft Windowsä. Superior performance is
also achieved through a direct 32-bit interface to the PCI Local Bus. The C&T65550 offers
exceptional performance when combined with CHIPS advanced linear acceleration driver
technology .
HARDWARE MULTIMEDIA SUPPORTThe C&T65550 implements independent multimedia capture (and display systems on-chip. The
capture system places data in display memory (usually off screen) and the display system places it
in a window on the screen.
The capture system can receive data from either the system bus or from the ZV enabled video
port in either RGB or YUV format. The input data can also scaled down before storage in display
memory (c.g., from any size larger than 320x240 down to 352x248). Capture of input data may
also be double buffered for smoothing and to prevent image tearing.
The display system can independently place either RGB or YUV data from any where in display
memory into an on-screen window which can be any size and located at any pixel boundary (YUV
data is converted to RGB on-the-fly on out put). Non-rectangular windows .are supported via
color keying. The data can be functionally zoomed on output up to 8x to fit the onscreen window
and can be horizontally and vertically inter polated to scale or zoom artifacts. Interlaced and non-
interlaced data are supported in both capture and display systems.
VERSATILE PANEL SUPPORTThe C&T65550 supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS)
and Dual-Panel, Dual Drive (DD) standard and high-resolution passive STN and active matrix
TFT/MIM LCD, and EL panels. For monochrome panels, up to 64 gray scales are supported. Up to
4096 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active
matrix LCDs. 
						

							Major Chips Description2-41The C&T65550 offers a variety of programmable features to optimize display quality. Vertical
centering and stretching are provided for handling modes with less than 480 lines on 480-line
panels. Horizontal and vertical stretching capabilities are also available for both text and graphics
modes for optimal display of VGA text and graphics modes on 800x600 and 1024x768 panels.
Three selectable color-to-gray scale reduction techniques and SMARTMAP™ are available for
improving the ability to view color applications on monochrome panels. CHIPS polynomial FRC
algorithm reduces panel flicker on a wider range of panel types with a single setting for a particular
panel type.
LOW POWER CONSUMPTIONThe C&T65550 employs a variety of advanced power management features to reduce power
consumption of the display sub-system and extend battery life. Although optimized for 3.3V
operation, The C&T65550 controllers internal logic. memory interface, bus interface, and panel
interfaces can he independently configured to operate at either 3.3V or 5V.
SOFTWARE COMPATIBILITY/FLEXIBILITYThe C&T65550 are fully compatible with VGA at the register, and BIOS levels. CHIPS and third-
party vendors supply fully VGA-compatible BIOS, end-user  utilities  and drivers for common
application programs
Pin names in parentheses (...) indicate alternate functions.
2.5.2Block DiagramMemory ControllerScalingCapture64-bit
Graphics
EngineYUV to RGB
Color Key ZoomBus InterfaceVideo
Capture
PortPCI BusAnalog
RGBDigital
RGBVideo MemoryFigure 2-9C&T 65550 Block Diagram 
						

							2-42Service Guide2.5.3Pin DiagramFigure 2-10C&T 65550 Pin Diagram 
						

							Major Chips Description2-432.5.4Pin Descriptions
Table 2-10C&T 65550 Pin DescriptionsPin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface207RESETInReset.  For VL-Bus interfaces, connect to RESET#.  For
direct CPU local bus interfaces, connect to the system reset
generated by the mother board system logic for all
peripherals (not the RESET# pin of the processor).  This
input is ignored during Standby mode (STNDIBY# pin low) so
that the remainder of the system (and the system bus) may
be safely powered down during Standby mode if desired.22ADS#InAddress Strobe.  In VL-Bus and CPU local bus interfaces
ADS# indicates valid address and control signal information
is present.  It is used for all decodes and to indicate the start
of a bus cycle.31M/IO#InMemory /IO.  In VL-Bus and CPU local bus interfaces M/lO#
indicates either a memory or an I/O cycle:
1 = memory, 0 = I/O11W/R#InWrite / Read.  This control signal indicates a write (high) or
read (low) operation.  It is sampled on the rising edge of the
(internal) 1x CPU clock when ADS# is active.23RDYRTN# for 1x Clock
config
CRESET for 2x Clock
configInReady Return.  Handshaking signal in VL-Bus interface
indicating synchronization of RDY# by the local bus master /
controller to the processor.  Upon receipt of this LCLK-
synchronous signal the chip will stop driving the bus (if a read
cycle was active) and terminate the current cycle.24LRDY#Out/
OCLocal Ready.  Driven low during VL-Bus and CPU local bus
cycles to indicate the current cycle should be completed This
signal is driven high at the end of the cycle, then tri-stated.
This pin is tri-stated during Standby mode (as are all other
bus interface outputs).25LDEV#OutLocal Device.  In VL Bus and CPU local bus interfaces. this
pin indicates that the chip owns the current cycle based on
the memory or l/O address which has been broadcast.  For
VL-Bus, it is a direct output reflecting a straight address
decode.  This pin is tri-stated during Standby mode (as are all
other bus interface outputs).27LCLKInLocal Clock.  In VL Bus this pin is connected to the CPU 1x
clock.  In CPU local bus interfaces it is connected to the CPU
1x or 2x clock.  If the input is a 2x clock, the processor reset
signal must be connected to CRESET (pin 23) for
synchronization of the clock phase.