Acer Extensa 610 Service Guide

							2-14Service Guide2.3ALI M1523
The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in
the DMA controller.  This chip contains the keyboard controller, real-time clock and IDE master
controller.  This chip also supports the Advanced Programmable Interrupt controller (APIC)
interface.
One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes.  One
32-bit wide posted-write buffer is provided for PCI memory write cycles to the ISA bus.  It also
supports a PCI to ISA IRQ routing table and level-to-edge trigger transfer.
The chip has two extra IRQ lines and one programmable chip select for motherboard Plug-and-
Play functions.  The interrupt lines can be routed to any of the available ISA interrupts.
The on-chip IDE controller supports two IDE connectors for up to four IDE devices providing an
interface for IDE hard disks and CD-ROMs.  The ATA bus pins are dedicated to improve the
performance of IDE master.
The M1523 supports the Super Green feature for Intel and Intel compatible CPUs.  It implements
programmable hardware events, software event and external switches (for suspend/turbo/ring-in).
The M1523 provides CPU clock control (STPCLKJ).  The STPCLKJ can be active (low) or inactive
(high) in turn by throttling control.
2.3.1Features
· Technology
· 0.6µm, triple-metal CMOS process
· Provides a bridge between the PCI bus and ISA bus
· PCI interface
· Supports PCI master and slave interface
· Supports PCI master and slave initiated termination
· PCI spec. 2.1 compliant (delay transaction support)
· Buffers
· 8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus
· 32-bit posted-write buffer for PCI memory write and I/O data write (for sound card) to ISA
bus
· Provides steerable PCI interrupts for PnP PCI devices
· Up to eight PCI interrupts routing
· Level-to-edge trigger transfer
· Enhanced DMA controller
· Provides seven programmable channels (four for 8-bit data size, three for 16-bit data
size) 
						

							Major Chips Description2-15· 32-bit addressability
· Provides compatible DMA transfers
· Provides type F transfers
· Interrupt controller
· Provides 14 interrupt channels
· Independently programmable level/edge triggered channels
· Counter/Timers
· Provides 8254 compatible timers for system timer, refresh request, speaker output use
· Keyboard controller
· Built-in PS2/AT keyboard controller
· The specific I/O is used to save the external TTL buffer
· Real time clock
· Built-in real-time clock
· 128-byte CMOS RAM with 2µA standby current maximum
· Plug-and-Play port support
· programmable chip select
· Steerable interrupt request lines
· PMU interface
· Supports CPU SMM mode, SMI feature
· Supports programmable stop clock throttle
· Supports the APM control
· Provides external suspend mode switch/turbo switch/ring-in switch
· Provides four system states for power saving (on, doze, standby, suspend)
· Provides three timers from 1 second to 300 minutes to individually monitor VGA, MODE,
IN status
· Supports RTC alarm wake up control
· IDE interface
· Built-in PCI IDE master controller
· Supports PIO modes up to mode 5 timings, and multiword DMA mode 0, 1, 2
· 8 x 32-bit pre-read and posted-write buffers
· Dedicated pins for ATA interface
· Supports up to 256 KB ROM size decode
· Reserved USB interface
· 208-pin PQFP package 
						

							2-16Service Guide2.3.2Block Diagram
M1523 Block DiagramDATA
Buffer
ControlAddress
BufferDecoderClock & ResetPCI BUS
Interface
UNITPCI
Arbiter
InterfaceISA
Interrupt
UNITPCI
Interrupt
UNITCPU
InterfaceUSB
Interface
(reserved)PCI
IDE
Master
InterfaceISA BUS
Interface
UNITDMA
Refresh
UNITPMU or APIC
InterfacePS2/AT
Keyboard
ControllerTimer
UNITMISC.
LogicREAL
Time
ClockPWG
CPURST
RSTDRV
OSC14MPCICLK
CBEJ[3:0]
AD[31:0]
FRAMEJ
TRDYJ
IRDYJ
STOPJ
DEVSELJ
SERRJ
PARPHOLDJ
PHLDAJFERRJ
IRQ[15:14]
IRQ[11:3]
INTAJ/M1II
NTBJ/S0
INTCJ/S1
INTDJ/S2IGNNEJ
INTR
NMI
A20MJ
USBCLK
USBP[11:10]
IDRQ[0:1]
IDAKJ[0:1]
IDERDY
IDEIORJ
IDEIOWJ
IDESCS3J
IDESCS1J
IDEPCS3J
IDEPCS1J
IDE_A[2:0]
IDE_D[15:0]SD[15:8]
XD[7:0]
SA[19:0]
SBHEJ
LA[23:17]
IO16J
M16J
MEMRJ
MEMWJ
AEN
IOCHRDYJ
NOWSJ
IOCHKJ
SYSCLK
BALE
IORJ
IOWJ
SMEMRJ/LMEGJ
SMEMWJ/RTCAS
EXTSW
STPCLKJSPKRSIRQI
XDIR
SPLED
ROMCSJSIRQII
RTC32KI
RTC32KIIKBINH/IRQ1
KBCLK/KBCSJ
KBDATA
MSCLK
IRQ12/MDATA
DREQ[7:5]
DREQ[3:0]
DACKJ[7:5]
DACK2J/3J
TC
REFSHJFigure 2-5M1523 Block Diagram 
						

							Major Chips Description2-172.3.3Pin Diagram                                                       VDD
IRQ12
MSCLK
KBDATA
KBCLK/KBCSJ
KBINH/IRQ1
IDESCS3J
IDESCS1J
IDEPCS3J
IDEPCS1J
IDE_A0
IDE_A2
IDE_A1
IDAKJ1
IDAKJ0
IDERDY
IDEIORJ
IDEIOWJ
IDRQ1
IDRQ0
IDE_D0
IDE_D15
Vss
IDE_D1
IDE_D14
IDE_D2
IDE_D13
IDE_D3
IDE_D12
IDE_D4
IDE_D11
IDE_D5
IDE_D10
IDE_D6
IDE_D9
IDE_D7
VDD
IDE_D8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CBEJ0
AD8
AD9
AD10
AD11
VDD Vss
BALE
SA2
SA1
SA0
SBHEJ
M16J
LA23
IO16J
LA22
IRQ10
LA21
IRQ11
VDD/BAT
RTC32KII
RTC32KI
PWG
LA20
LA19
IRQ15
LA18
IRQ14
LA17
MEMRJ
DREQ0
Vss
MEMWJ
DACK5J
SD8
DREQ5
SD9
DACK6J
SD10
DREQ6
SD11
DACK7J
SD12
DREQ7
SD13
VDD
SD14
SD15
OSC14M
SIRQI
SIRQII
USBCLK
DACK0J
DACK1J
CPURST
SMIJ
STPCLKJ
Vss 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105 ALiM1523Figure 2-6M1523 Pin Diagram 
						

							2-18Service Guide2.3.4Signal Descriptions
Table 2-3M1523 Signal DescriptionsSignalPinTypeDescriptionClock and ResetPWG17IPower-Good Input.  This signal comes from the power
supply to indicate that power is available and stable.CPURST49OCPU Reset includes cold and warm reset 3.3V signal
(connected to CPU INIT)RSTDRV57OCPU Cold Reset.  3.3V signal (connected to CPU RESET)OSC14M43I14.318Mhz Clock Input.  This is used for 8254 timer clock.PCI InterfacePCICLK71IPCI clock for internal PCI interface.AD[31:0]73-80, 83-90,
100-104, 106-
109, 111-118I/OAddress and Data are multiplexed on PCI bus.   During
the first clock of a PCI transaction, AD[31-0] contains a
physical address.  During subsequent clocks, AD[31-0]
contains data.C/BEJ[3:0]81, 91, 99,
110I/OBus Command and Byte Enable.  During address phase,
CBEJ[3:0] define the bus command.  During data phase,
CBEJ[3:0] define the byte enables.FRAMEJ92I/OCycle Frame.  is driven by current initiator to indicate the
beginning and duration of an access.DEVSELJ95I/ODevice Select. .  This indicates that the target device has
decoded the address as its own cycle.  This pin is an
output pin when the M1523 acts as a PCI slave that has
decoded address as its own cycle including subtractive
decoding.IRDYJ93I/OInitiator Ready indicates the initiator’s ability to complete
the current data phase of the transaction.TRDYJ94I/OTarget Ready indicates the targets ability to complete the
current data phase of the transaction.STOPJ96I/OStop indicates to the M1523 is requesting a master to stop
the current transaction.PAR98I/OParity Signal.  PAR is even parity and is calculated on
AD[31:0] and CBEJ[3:0].  When the M1523 acts as a PCI
master, it drives PAR one PCI clock after address phase
for a read/write transaction and one PCI clock after data
phase for a write transaction.  When the M1523 acts as
target, it drives PAR one PCI clock after data phase for a
PCI master read transaction.SERRJ97ISystem Error may be pulsed active by any agent  that
detects a system error condition.  When SERRJ is
sampled low, the M1523 asserts NMI to send an interrupt
to the CPU. 
						

							Major Chips Description2-19Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionPCI Interrupt UnitINTAJ_MI67IPCI Interrupt Input A or PCI interrupt polling input.INTBJ68I/OPCI Interrupt Input B or polling select_0 output.INTCJ69I/OPCI Interrupt Input C or polling select_1 output.INTDJ70I/OPCI Interrupt Input D or polling select_2 output.PCI ArbiterPHOLDJ66OM1523 requests the ownership of the PCI bus.
  Hardware setting option
  Pull low : internal RTC is enabled
  Pull high : external RTC is used.PHLDAJ65IPCI Hold Acknowledge.  When this pin is asserted, the
M1523 owns the PCI bus.CPU Interface (3.3V)IGNNEJ55OIgnore Numeric Error. This pin is used as the ignore
numeric coprocessor error.INTR54OInterrupt Request to CPU.  This is the interrupt signal
generated by the internal 8259.NMI58ONon-maskable Interrupt.  This is non-maskable interrupt
request to CPU.A20MJ56OCPU A20 Mask.  This is the address line 20 mask signal.ISA InterfaceFERRJ/IRQ1362IFloating Point Error.  FERRJ input to generate IRQ13.
When the coprocessor interface is disabled in
configuration port 43h bit 6, the function of this pin is
IRQ13.IRQ12 / MDATAO155I/OMouse Interrupt Request Input/Mouse Data Output.  When
internal PS/2 keyboard is disabled, this pin is mouse
interrupt input.  Otherwise, this pin is mouse data output.IRQ[15:14],
IRQ[11:9],
IRQ[7:3]20, 22, 13, 11,
164, 194, 196,
200, 202IInterrupt Request Signals.SD[15:8]42, 41, 39, 37,
35, 33, 31, 29I/OISA High-byte Slot Data Bus.  These lines are system data
lines.XD[7:0]161-163, 165,
167, 168, 170-
171I/OExternal Data Bus lines connect to SD[7:0] by an external
TTL LS245, whose direction is controlled by the M1523
output signal XDIR.SA19175OISA Slot Address Bus A19.SA18177OISA Slot Address Bus A18.SA17179OISA Slot Address Bus A17. 
						

							2-20Service GuideTable 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionISA InterfaceSA[16:0]181, 185, 187,
188, 190, 192,
193, 195, 197,
199, 201, 203,
205, 207, 3, 4,
5I/OISA Slot Address Bus.  These lines are addresses
connected to slot address.SBHEJ6I/OISA Slot Byte-high Enable.  In a CPU or PCI master cycle,
this signal is generated by BE3J-BE0J and the chip’s
internal control circuit.  In a DMA cycle, it is generated by
internal 8237.  In a refresh cycle, it is generated by the
internal refresh circuits.  It is an input signal for ISA
master cycle.LA[23:17]8, 10, 12, 18,
19, 21, 23I/OISA Latched Address Bus. They are input during ISA
master cycle.IO16J9IISA 16-bit I/O Device Indicator.  This signal indicates the
I/O device supports 16-bit transfers.M16J7I/OISA 16-bit Memory Device Indicator.  This signal indicates
the memory device supports 16-bit transfers.MEMRJ24I/OISA Memory Read.  This signal is an input during ISA
master cycle.MEMWJ27I/OISA Memory Write.  This signal is an input during ISA
master cycle.AEN173OISA I/O Address Enable.  Active high signal during DMA
cycle to prevent I/O device from misinterpreting the DMA
cycle as valid I/O cycle.IOCHRDY172I/OISA System Ready. This signal is an output during
ISA/DMA master cycle.NOWSJ169IISA Zero-wait State for Input.  This signal terminates the
CPU to ISA command instantly.IOCHKJ160IISA Parity Error.  M1523 generates NMI to CPU when this
signal is asserted.SYSCLK183OISA System Clock.  This signal provides clocking function
to ISA bus.BALE2OBus Address Latch Enable.  BALE is active throughout
DMA and ISA master and refresh cycles.IORJ180I/OISA I/O Read. This signal is an input during ISA master
cycle.IOWJ178I/OISA I/O Write. This signal is an input during ISA  master
cycle. 
						

							Major Chips Description2-21Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionISA InterfaceSMEMRJ / LMEGJ176OISA System Memory Read.  When the internal RTC is
enabled, this signal indicates that the memory read cycle
is for an address below 1-MB address.  Otherwise, this pin
only indicates an address below 1M byte.SMEMWJ / RTCAS174OISA System Memory Write.  When the internal RTC is
enabled, this signal indicates that the memory write cycle
is for an address below 1-MB address.  Otherwise, this pin
is used as RTC address strobe.DREQJ[7:5]
DREQJ[3:0]38, 34, 30,
186, 166, 189,
25IDMA Request Signals.  These are DMA request input
signals.DACKJ[7:5] /
DAK_SEL[2:0]
DACKJ[3] / PCSJ,
DACKJ[2] /
DACKOJDACKJ[1],
DACKJ[0]36,32,
28,
184,
204,
48,
47O
I/O
OWhen DACKJ polling mode is disabled, these pins are
DACKJ[7:5,3:0](O).  Otherwise, these pins are
DAK_SEL[2:0](O) connect to external MUX select inputs,
PCSJ(O) programmable chip select, and DACKOJ(O)
connected to external MUX chip enable.TC206ODMA End of Process.  Hardware setting options:
Pulled low:  Support external I/O APIC mode
Pulled high:  Not support external I/O APICREFSHJ191I/OISA Refresh Cycle.  This signal is input during ISA master
cycles, but an output during other cycles.TimerSPKR43OSpeaker Output.  Hardware setting options:
Pulled low:  Enable Internal KBC
Pulled high:  Disable Internal KBCMiscellaneousSPLED44OSpeed LED Output.  Hardware setting options:
Pulled low:Enable DMA DACKJ[7:5,3:0]
polling mode
Pulled high:Disable DMA DACKJ[7:5;3:0]
polling modeROMCSJ158OROM and RTC Chip Select.  This signal must be pulled
high for normal operation.XDIR159OX-bus Direction Control.  Hardware setting option: must be
pulled high.KBINH/ IRQ1151IKB Inhibit Input when the internal KBC is enabled.
IRQ1 Input when the internal KBC is disabledKBCLK/ KBCSJ152I/OKB interface CLK when the internal KBC is enabled.
KB Chip Select when the internal KBC is disabledKBDATA153OKB interface Data when the internal KBC is enabled. 
						

							2-22Service GuideTable 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionMiscellaneousMSCLK154OMouse Clock Output when the internal KBC is enabled.RTC32KI16IRTC 32.768K Osc1.  This is crystal input and requires an
external 32.768khz quartz crystal.RTC32KII15IRTC 32.768K Osc2.  This is crystal input and requires an
external 32.768khz quartz crystal.SIRQI44ISteerable IRQ Input 1SIRQII/IRQ8J45ISteerable IRQ Input 2 when the internal RTC is enabled.
RTC interrupt input when the internal RTC is disabled.USBCLK46IUniversal serial bus clock pin (reserved).USBP1[1:0]59, 60I/OUniversal serial bus data pin (reserved).Power ManagementEXTSW /
APICREQJ61IExternal SMI Switch or APIC Request Input.  EXTSW is a
falling edge triggered input to the M1523 showing that an
external device is requesting the system to enter SMM
mode.  An external pull-up should be placed on this signal
if it is not used or it is not guaranteed to be always driven.
When external APIC mode is enabled, this pin is
APICREQJ.SMIJ / APICCSJ50OSMM Interrupt or APIC Chip Select.  A synchronous
output asserted by the M1523 in response  to one of many
enabled hardware or software events. When external APIC
mode is enabled, this pin is APICCSJ.STPCLKJ /
APICGNTJ51OStop CPU Clock Request or APIC Grant Output.
STPCLKJ is connected directly to the CPU and is
synchronous with PCI clock. When external APIC mode is
enabled, this pin is APICGNTJ.IDE InterfaceIDRQ[1:0]138-137IIDE DRQ Request for IDE MasterIDAKJ[1:0]143-142OIDE DACKJ for IDE MasterIDERDY141IIDE ReadyIDEIORJ140OIDE IORJ CommandIDEIOWJ139OIDE IOWJ CommandIDESCS1J149OIDE chip Select for Secondary Channel 0IDESCS3J150OIDE chip Select for Secondary Channel 1IDEPCS1J147OIDE chip Select for Primary Channel 0IDEPCS3J148OIDE chip Select for Primary Channel 1IDE_A[2:0]145, 144, 146OIDE ATA Address Bus 
						

							Major Chips Description2-23Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionIDE InterfaceIDE_D[15:0]135, 132, 130,
128, 126, 124,
122, 119, 121,
123, 125, 127,
129, 131, 133,
136I/OIDE ATA Data BusVcc and VssVCC353PVcc 3.3VVCC5/VBAT14PRTC Battery InputVCC540, 72, 105,
120, 156, 208PVCC 5.0V(VDD)Vss1, 26, 52, 82,
104, 134, 157,
182PVss or Ground.