Acer Extensa 610 Service Guide

							2-4Service Guide2.2.2Block Diagram586
CPUSRAMM1521
BGADRAMHDDM1523UMA
Graphic
controllerIDE Master
Aladdin III System Block DiagramCDCPU BusPCI BusISA BusUSB connectorFigure 2-1Alladin III Block Diagram 
						

							Major Chips Description2-52.2.3System ArchitectureM1521M1523ALADDIN-III SYSTEM ARCHITECTUREtag 8/11-bitTTLSRAM
208-PQFP/RTC/KBC328-BGA586 CPU
addrdataPCIISADRAM MDGCMA
CTLRIDE bus
HDD128K/256K
FlashXD - TTLUSB connFigure 2-2Alladin III System Architecture 
						

							2-6Service Guide2.2.4Data PathE C C64-bitSWAPHD_
OUT64-bitSWAP6 DWORD5 DWORD6 DWORDMUXPCI_OUTPCI_INP_IN[31:0]PB_OUT[63:0]64-bitHDIN[63:0]MUX72-bitECC72-bitSWAP8 QWORDMUXMUXMUXMDIN[63:0]PCI_INMD_IN[63:0]PB_IN[63:0]HD_INSWAPH/L DW swapfor 32-bit DRAMMD_OUTM1521MD_INECC partial
W-R pathFigure 2-3M1521 Data Path 
						

							Major Chips Description2-72.2.5Pin DiagramFigure 2-4M1521 Pin Diagram 
						

							2-8Service Guide2.2.6Signal Descriptions
Table 2-2M1521 Signal DescriptionsSignalPinTypeDescriptionHost InterfaceA[31:29]
A[28:26]
A[25:23]
A[22:20]
A[19:17]
A[16:14]
A[13:11]
A[10:08]
A[07:05]
A[04:03]W8, W11, U11, Y10,
Y9, V10, W9, W10, U9,
U10, V9, U5, V5, W5,
Y5, U6, W6, V6, Y6,
U7, W7, Y7, V7, V8,
Y8, Y12, U8, Y11, V11I/OHost Address Bus Lines.  A[31:3] have two
functions.  As inputs, along with the byte enable
signals, these serve as the address lines of the host
address bus that defines the physical area of
memory or I/O being accessed.  As outputs, the
M1521 drives them during inquiry cycles on behalf of
PCI masters.BEJ[7:0]M1, L4, L3, L2, L1, K4,
K3, K2IByte Enables.  These are the byte enable signals for
the data bus.  BEJ[7] applies to the most significant
byte and BEJ[0] applies to the least significant byte.
They determine which byte of data must be written to
the memory, or are requested by the CPU.  In local
memory read and line-fill cycles, these are ignored
by the M1521.ADSJT5IAddress Strobe.  The CPU or M1521 starts a new
cycle by asserting ADSJ first.  The M1521 does not
precede to execute a cycle until it detects ADSJ
active.BRDYJM5OBurst Ready.  The assertion of BRDYJ means the
current transaction is complete.  The CPU
terminates the cycle by receiving 1 or 4 active
BRDYJs depending on different types of cycles.NAJN5ONext Address.  It is asserted by the M1521 to inform
the CPU that pipelined cycles are ready for
execution.AHOLDL5OCPU A-Hold Request Output.  It serves as the input
of CPUs AHOLD pin and actively driven for inquiry
cycles.EADSJR5OExternal Address Strobe.  This signal is connected to
the CPU EADSJ pin.  During PCI cycles, the M1521
asserts this signal to proceed snooping.BOFFJP5OCPU Back-Off.  If BOFFJ is sampled active, CPU
floats all its buses in the next clock.HITMJT8IHost Cache Hit after Modified.  When snooped, the
CPU asserts HITMJ to indicate that a hit to a
modified line in the data cache occurred.  It is used
to prohibit another bus master from accessing the
data of this modified line in the memory until the line
is completely written-back. 
						

							Major Chips Description2-9Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionHost InterfaceM/IOJH5IHost Memory or I/O.  This bus definition pin
indicates the current bus cycle is either memory or
input/ output.D/CJT7IHost Data or Code.  This bus definition pin is used to
distinguish data access cycles from code access
cycles.W/RJT9IHost Write or Read.  When WRJ is driven high, it
indicates the current cycle is a write.  Inversely, if
WRJ is driven low, a read cycle is performed.HLOCKJG5IHost Lock.  When HLOCKJ is asserted by the CPU,
the M1521 recognizes that the CPU is locking the
current cycles.CACHEJJ5IHost Cacheable.  This pin is used to indicate the
host’s internal cacheability of the read cycles.  If it is
driven inactive, the CPU does not cache the returned
data regardless of the state of KENJ.KENJ/INVK5OCache Enable Output.  This signal connects to the
CPUs KENJ and INV pins.  KENJ is used to notify
the CPU whether the address of the current
transaction is cacheable.  INV is used during L1
snoop cycles.  The M1521 drives this signal high
(low) during the EADSJ assertion of a PCI master
write (read) snoop cycle.SMIACTJT10ISMM Interrupt Active.  It is asserted by the CPU to
inform the M1521 that SMM mode is being entered.HD[63:0]A1, B1, C3, C2, C1, D2,
D3, E3, D1, E2, E4, E1,
F3, F4, G3, F1, F2, H3,
G1, H4, G4, J3, G2,
H2, H1, J4, J1, J2, M4,
K1, M2, M3, N4, N2,
N3, P4, N1, P2, P3, R4,
P1, T2, R2, T4, R3, U2,
T3, U4, V2, U3, V4, T1,
W4, V3, W3, U1, R1,
V1, W2, W1, Y4, Y2,
Y3, Y1I/OHost Data Bus Lines.  These signals connect to the
CPUs data bus.DRAM InterfaceMPD[7:0]G18, H20, G20, H18,
F20, J18, G19, H19I/ODRAM Parity/ECC check bits.  These are the 8-bit
parity/ECC check bits over DRAM bus.RASJ[7] /
SRASJ[0]N16ORow Address Strobe 7 or Synchronous DRAM RAS
0. FPM/EDO/BEDO of DRAM bank 7.  SDRAM row
address strobe (SDRAM) copy 0. 
						

							2-10Service GuideTable 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionDRAM InterfaceRASJ[6] /
SCASJ[0]M16ORow Address Strobe 6, or Synchronous DRAM CAS
0 (FPM/EDO/BEDO) of DRAM bank 6. SDRAM
column address strobe (SDRAM) copy 0.RASJ[5:0] /
SCSJ[5:0]N17, M17, E16, F16,
F17, G17I/ORow Address Strobes or synchronous DRAM chip
select.  These signals drives the corresponding
RASJs of DRAMs or synchronous DRAM chip
select[5:0].CASJ[7:0] /
DQM[7:0]L16, G16, J16, H16,
L17, H17, K17, J17OColumn Address Strobes or Synchronous DRAM
Input/Output Data Mask.  These CAS signals should
connect to the corresponding CASJs of each bank of
DRAM.  The value of CASJs equals that of HBEJs
for write cycles.  During DRAM read cycles, all the
CASJs are active.  In SDRAM, these pins act as
synchronized output enables during a read cycle and
a byte mask during a write cycle.MA[11:2]V14, Y14, Y15, U14,
W14, T13, U13, V13,
W13, Y13ODRAM Address lines.  These signals are the address
lines of all DRAMs.  The M1521 supports DRAM
types ranging from 256K to 64M.MAA[1:0]T12, V12OMemory Address copy A for [1:0]MAB[1:0]U12, W12OMemory Address copy B for [1:0]MD[63:0]C15, A16, B17, A18,
B19, B20, D19, E20,
J19, K20, M18, N19,
P20, R19, T18, V20,
C14, D15, C16, D17,
A20, C20, E18, F19,
K18, L19, M20, P18,
R17, T20, U19, V19,
B14, D16, A17, C17,
A19, D18, E17, E19,
J20, L18, M19, N20,
P17, R18, U20, U18,
C13, B15, B16, B18,
C18, C19, C20, F18,
K19, L20, N18, P19,
R20, T19, T17, W20I/OMemory Data.  These pins connect to DRAMs.MWEJ[0]T11ODRAM Write Enable.  This is the DRAM write enable
pin and behaves according to the early-write
mechanism; i.e. it activates before the CASJs do.
For refresh cycles, it remains deasserted.Secondary Cache InterfaceCADVJ/CA4V15OSynchronous SRAM advance or Asynchronous
SRAM address line 4.CADSJ/CA3W15OSynchronous SRAM address strobe cache or
Asynchronous SRAM address line 3. 
						

							Major Chips Description2-11Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionSecondary Cache InterfaceCCSJ/CB4W16OSynchronous SRAM chip select or Cache Address
line 4 copy.  This pin has two modes of operation
depending on the type of SRAM selected via
hardware strapping options or programming the CC
register.GWEJY16OSynchronous SRAM Global Write Enable or
Asynchronous SRAM Write Enable.COEJU15OSynchronous/Asynchronous SRAM Output Enable.BWEJ/CGCSJY17OSynchronous SRAM Byte-Write Enable/
Asynchronous SRAM Global Chip Select.TIO[10]/
MWEJ[1]Y20I/OSRAM Tag[10] or another copy of MWEJ.TIO[9]/
SRASJ[1]Y19I/OSRAM Tag[9] or synchronous DRAM (SDRAM) RAS
copy 1.TIO[8]/
SCASJ[1]W19I/OSRAM Tag[8] or synchronous DRAM (SDRAM) CAS
copy 1.TIO[7:0]Y18, W18, V18, T14,
V17, U17, U16, P16I/OSRAM Tag[7:0].  This pin contains the L2 tag
address for 256 KB L2 caches.  TIO[6:0] contain the
L2 tag address and TIO7 contains the L2 cache valid
bit for 512 KB  caches.TWEJV16OTag Write Enable.  This signal, when asserted,
writes into the external tag new state and tag
addresses.PCI InterfaceAD[31:28]
AD[27:24]
AD[23:20]
AD[19:16]
AD[15:12]
AD[11:08]
AD[07:04]
AD[03:00]A2, B2, A3, B3, A4, B4,
C4, D6, B5, C5, A6, B6,
C6, A7, B7, C7, C8, A9,
B9, C9, A10, B10, C10,
A11, C11, A12, B12,
C12, A13, B13, A14,
A15I/OPCI Address-and-Data Bus Lines.  These lines
connect to the PCI bus. AD[31:0] contain the
information of address or data for PCI transactions.CBEJ[3:0]A5, A8, B8, B11I/OPCI Bus Command and Byte Enables.  Bus
commands and byte enables are multiplexed in
these lines for address and data phases,
respectively.FRAMEJE6I/OCycle Frame of PCI Buses.  This indicates the
beginning and duration of a PCI access.DEVSELJE9I/ODevice Select.  When the target device has decoded
the address as its own cycle, it asserts DEVSELJ.IRDYJE7I/OInitiator Ready.  This indicates the initiator is ready
to complete the current data phase of transaction. 
						

							2-12Service GuideTable 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionTRDYJE8I/OTarget Ready.  This indicates the target is ready to
complete the current data phase of transaction.STOPJE11I/OStop.  This indicates the target is requesting the
master to stop the current transaction.LOCKJE5I/OLock Resource Signal.  This indicates the PCI
master or the bridge intends to do exclusive
transfers.REQJ[3:0]D13, D11, D9, D7IBus request signals of PCI Masters.  When asserted,
it means the PCI master is requesting the PCI bus
ownership from the arbiter.GNTJ[3:0]D14, D12, D10, D8OGrant signals to PCI Masters.  When asserted by the
arbiter, it means the PCI master has been legally
granted to own the bus.PHLDJD4IPCI bus hold request.  This active low signal is a
request from M1523 for the PCI bus.PHLDAJD5OPCI bus hold acknowledge.  This active low signal
grants PCI to M1523.PARE12I/OParity bit of PCI buses.  It is the even parity bit
across PAD[31:0] and CBEJ[3:0].SERRJE13OSystem Error.  If the M1521 detects parity errors in
DRAMs, it asserts SERRJ to notify the system.Clock, Reset, and Suspend InterfacesRSTJT15ISystem Reset.  This pin, when asserted, resets the
M1521 and sets the register bits to their default
values.SUSPENDJP6ISuspend.  When actively sampled, the M1521 enters
the I/O suspend mode.  This signal should be pulled
high when the suspend feature is disabled.HCLKINK16ICPU Bus Clock Input.  This signal is used by all of
the M1521 logic that is in the host clock domain.PCLKINE10IPCI Bus Clock Input.  This signal is used by all of
the M1521 logic that is in the PCI clock domain.32KW17IThe refresh reference clock of frequency 32khz
during suspend mode.  This signal should be pulled
to a fixed value when the suspend feature is
disabled.UMA InterfaceMREQJ/
REQJ[4]H6IMemory Request.  This input signal is from the GUI
device’s MREQJ output.  This pin can also be used
as bus request signal of the fifth PCI master. 
						

							Major Chips Description2-13Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionUMA InterfaceMGNTJ/
GNTJ[4]F7OMemory Grant.  This output connects to the MGNTJ
of the GUI device.   This pin can also be used as
grant signal of the fifth PCI master.PRIOG15IPriority.  The high priority request from the GUI
device.Power PinsVCCF5, F6, G6, R6, R7,
F14, F15, P15, R15,
R16PVcc 3.3VVDD_5E14PVcc 5.0VVss or GndE15, T16, J9, J10, J11,
J12, K9, K10, K11,
K12, L9, L10, L11, L12,
M9, M10, M11, M12PGround