Acer Extensa 610 Service Guide

							2-44Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface (continued)43BE0# (BLE#)InByte Enable 0. Indicates data transfer on D7:D0 for the
current cycle.32BE1#InByte Enable 1. Indicates data transfer on D15:D8 for the
current cycle.21BE2#InByte Enable 2. Indicates data transfer on D23:D16 for the
current cycle.10BE3#InByte Enable 3. BE3# indicates that data will transfer over the
data bus on D31 :24 during the current access.179
180
182
183
185
186
187
188
189
190
191
192
193
194
195
196
197
189
199
200
201
28
29
30
53
54A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
InSystem Address Bus.  In VL-Bus, and direct CPU interfaces,
the address pins are connected directly to the bus.  In internal
clock synthesizer test mode (TS# = 0 at Reset), A24
becomes VCLK out and A25 becomes MCLK out.  A26 and
A27 may be alternately used as General Purpose I/O pins or
as Activity Indicator and Enable Backlight respectively (see
panel interface pin descriptions, and FROF and FROC for
more details).  If A26 and A27, are used as GPIO pins, they
may be programmed as a 2-pin CRT Monitor DDC interface
(VESA™ Display Data Channel also referred to as the
Monitor Plug-n-Play interface).  Either A26 or A27 may also
be used to output, Composite Sync for support of an external
NTSC / PAL encoder chip. 
						

							Major Chips Description2-45Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface (continued)51
50
49
48
47
46
45
44
41
40
38
37
36
35
34
33
20
19
18
17
16
15
14
13
8
7
6
5
4
3
2
1D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OSystem Data Bus.  In 32-bit CPU Local Bus designs these
data lines connect directly to the processor data lines.  On
the VL-Bus they connect to the corresponding buffered or
unbuffered data signal.  These pins are tri-stated during
Standby mode (as are all other bus interface outputs).PCI Bus Interface207RESET#InReset.  This input sets all signals and registers in the chip to
a known state.  All outputs from the chip are tri-stated or
driven to an inactive state.  This pin is ignored during
Standby mode (STNDBY# pin low).  The remainder of the
system (therefore the system bus) may be powered down if
desired (all bus output pins are tri-stated in Standby mode).201CLKInBus Clock.  This input provides the timing reference for all
bus transactions.  All bus inputs except RESET# and INTA#
are sampled on the rising edge of CLK.  CLK may be any
frequency from DC to 33MHz. 
						

							2-46Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)31PARI/OParity.  This signal is used to maintain even parity across
AD0-31 and C/BE0-3#.  PAR is stable and valid one clock
after the address phase.  For data phases, PAR is stable and
valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one clock after the
completion of the current data phase (i.e., PAR has the same
timing as AD0-31 but delayed by one clock).  The bus master
drives PAR for address and write data phases; the target
drives PAR for read data phases.22FRAME#InCycle Frame.  Driven by the current master to indicate the
beginning and duration of an access.  Assertion indicates a
bus transaction is beginning (while asserted, data transfers
continue); de-assertion indicates the transaction is in the final
data phase.23IRDY#InInitiator Ready.  Indicates the bus masters ability to complete
the current data phase of the transaction.  During a write,
IRDY# indicates valid data is present on AD0-31; during a
read it indicates the master is prepared to accept data.  A
data phase is completed on any clock when both IRDY# and
TRDY# are sampled then asserted (wait cycles are inserted
until this occurs).24TRDY#S/TSTarget Ready.  Indicates the targets ability to complete the
current data phase of the transaction.  During a read, TRDY#
indicates that valid data is present on AD0-31; during a write
it indicates the target is prepared to accept data.  A data
phase is completed on any clock when both IRDY# and
TRDY# are sampled then asserted (wait cycles are inserted
until this occurs).27STOP#S/TSStop.  Indicates the current target is requesting the master to
stop the current transaction25DEVSEL#S/TSDevice Select.  Indicates the current target has decoded its
address as the target of the current access29PERR# (VCLKOUT)S/TSParity Error.  This signal reports data parity errors (except the
Special Cycles where SERR# is used).  The PERR# is
Sustained Tri-state.  The receiving agent will drive PERR#
active two clocks after detecting a data parity error.  PERR#
will be driven high for one clock before being tri-stated as with
all sustained tri-state signals.  PERR# will not report status
until the chip has claimed the access by asserting DEVSEL#
and completing the data phase. 
						

							Major Chips Description2-47Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)30SERR# (MCLKOUT)ODSystem Error.  Used to report system errors where the result
will be catastrophic (address parity error, data parity errors
for Special Cycle commands, etc.).  This output is actively
driven for a single PCI clock cycle synchronous to CLK and
meets the same setup and hold time requirements as all
other bused signals.  SERR# is not driven high by the chip
after being asserted, but is pulled high only by a weak pull-up
provided by the system.  Thus, SERR# on the PCI Bus may
take two or three clock periods to fully return to an inactive
state.179
180
189
183
185
187
189
191
193
180
188
193
194
196
197
198ROMA0
ROMA1(GPIO3)
ROMA2(GPIO4)
ROMA3(GPIO5)
ROMA4(GPIO6)
ROMA5
ROMA6
ROMA7
ROMA8
ROMA10(GPIO7)
ROMA11
ROMA12
ROMA13
ROMA14
ROMA16
ROMA17Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
OutBlOS ROM Address Outputs.  See MAD8-15 (pins 170-177)
for BIOS ROM data inputs.
BIOS ROMs are not normally required in portable computer
designs (Graphics System BIOS code is normally included in
the System BIOS ROM).  However, the 65550 provides BIOS
ROM interface capability for development systems and add-in
card Flat Panel Graphics Controllers.
Since the PCI Bus specifications require only one load on the
bus for the entire graphics subsystem, the BlOS ROM
interface is through the chip.  In the VL-Bus mode. the BIOS
ROM interface can be an external circuit on the ISA Bus
connector that does not require pins on the chip.200ROMOE#OutBlOS ROM Output Enable.199ReservedInThis pin is always an input (A20 for VL-Bus, reserved for
future use on PCI Bus).  To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a 10K resistor to ground
to pull this pin low..28ReservedInThis pin is always an input (A23 for VL-Bus, reserved for
future use on PCI Bus). To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a l0K resistor to ground
to pull this pin low. 
						

							2-48Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)51
50
49
48
47
46
45
44
41
40
38
37
36
35
34
33
20
19
18
17
16
15
14
13
8
7
6
5
4
3
2
1AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OPCI Address / Data Bus.  Address and data are multiplexed
on the same pins.  A bus transaction consists of an address
phase followed by one or more data phases (both read and
write bursts are allowed by the bus definition).
The address phase is the clock cycle in which FRAME# is
asserted (AD0-31 contain a 32-bit physical address).  For I/O,
the address is a byte address; for memory and configuration,
the address is a DWORD address.  During data phases AD0-
7 contain the LSB and 24-31 contain the MSB.  Write data is
stable and valid when IRDY# is asserted; read data is stable
and valid when TRDY# is asserted.  Data transfers only
during those clocks when both IRDY# and TRDY# are
asserted. 
						

							Major Chips Description2-49Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)43
32
21
10C/BE0#
C/BE1#
C/BE2#
C/BE3#In
In
In
InBus Command / Byte Enables. During the address phase. of
a bus transaction, these pins define the bus command see
list below:
C/BE3-0              Command Type                        655500000Interrupt Acknowledge
0001Special Cycle
0010I/O ReadY
0011I/O WriteY
0100-reserved-
0101-reserved-
0110Memory ReadY
0111Memory WriteY
1000-reserved-
1001-reserved-
1010Configuration ReadY
1011Configuration WriteY
1100Memory Read Multiple
1101Dual Address Cycle
1110Memory Read Line
1111Memory Read & Invalidate
During the data phase, these pins are byte enables that
determine which byte lanes carry meaningful data:
byte 0 corresponds to AD0-7,
byte 1 corresponds to 8-15,
byte 2 corresponds to 16-23,
byte 3 corresponds to 24-3111IDSELInitialization.  Device Select.  Used as a chip select during
configuration read and write transactions.145
146
147
148
149
150
151
152
153AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OAddress bus for DRAMs A and B. 
						

							2-50Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)90
91
92
93
94
95
96
97
98CA0 (P16)
CA1 (P17)
CA2 (P18)
CA3 (P19)
CA4 (P10)
CA5 (P21)
CA6 (P22)
CA7 (P23)
CA8 (BLANK)Out
Out
Out
Out
Out
Out
Out
Out
I/OAddress bus for DRAM C.
CA0-7 may be configured as flat panel data output (P16-23).
See also pins 71-88 (in Flat Panel Display interface pin
descriptions section).
CA8 may be configured as VAFC BLANK# out or vertical
reference input (VREF) for video capture.99HREFInHorizontal reference input for video capture.156RASA# (RASAB0#)OutRAS for DRAM A (or bank 0 in 2MB configurations)123RASB# (RASAB1#)OutRAS for DRAM B (or bank 1 in 2MB configurations)101RASC# (VRDY)
             (KEY)Out
InRAS for DRAM C (or color key input from external PC-Video
source or VAFC Video System Ready input)160CASAL#OutCAS for the DRAM A lower byte159CASAH#OutCAS for the DRAM A upper byte126CASBL#OutCAS for the DRAM B lower byte125CASBH#OutCAS for the DRAM B upper byte104CASCL# (WECL#)
(VR6/VP14)I/ODRAM C low byte CAS (or video in red-6 or VAFC VP14)103CASCH# (CASC#)
(VR7/VP15)I/ODRAM C high byte CAS (or video in red-7 or VAFC VP15)157WEA# (WEAH#)
(WEAB0#)OutWrite enable for DRAM A (or bank 0 in 2MB)124WEB# (WEBH#)
(WEAB1#)OutWrite enable for DRAM B (or bank 1 in 2MB)102WEC# (WECH#)
(PCLK)OutWrite enable for DRAM C (or video in port PCLK out)155OEAB0#OutOutput enable for DRAMs A and B, bank 0, 1 of 2MB100OEC#
(VCLK)Out
InOutput enable for DRAM C (or VAFC Video Input Clock if
DRAM C not used) 
						

							Major Chips Description2-51Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionDisplay Memory Interface162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177MAD0
MAD1
MAD2 (CFG10)
MAD3 (CFG11)
MAD4 (CFG12)
MAD5 (CFG13)
MAD6 (CFG14)
MAD7 (CFG15)
MAD8 (PCI ROMD0)
MAD9 (PCI ROMD1)
MAD10 (PCI ROMD2)
MAD11 (PCI ROMD3)
MAD12 (PCI ROMD4)
MAD13 (PCI ROMD5)
MAD14 (PCI ROMD6)
MAD15 (PCI ROMD7)I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OMemory data bus for DRAM A.  (lower 512KB of display
memory)
MAD2-7 are latched into XR71 register on reset for use as
additional configuration inputs (CFG10-12 are reserved by
software for input of panel ID).  These bits have no other
internal hardware configuration function.
PCI Bus: MAD8-15 are used as BIOS ROM Data inputs
during system startup (i.e., before the system enables the
graphics controller memory interface).  See also pins 179-199
(in PCI Bus interface pin descriptions section) for BIOS ROM
address and ROAM Chip Select outputs.  In the VL-Bus
mode, the BIOS ROM interface can be an external circuit on
the ISA Bus connector.127
128
129
130
131
132
133
134
135
136
137
138
140
141
143
144MBD0
MBD1
MBD2
MBD3
MBD4
MBDS
MBD6
MBD7
MBD8
MBD9
MBD10
MBD11
MBD12
MBD13
MBD14
MBD15I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OMemory data bus for DRAM B (upper 512KB)106
107
109
110
111
112
113
114
115
116
117
118
119
120
121
122MCD0 (VB2) (EVID#)
MCDI (VB3) (VP0)
MCD2 (VB4) (VP1)
MCD3 (VB5) (VP2)
MCD4 (VB6) (VP3)
MCD5 (VB7) (VP4)
MCD6 (VG2) (VP5)
MCD7 (VG3) (VP6)
MCD8 (VG4) (VP7)
MCD9 (VG5) (VP8)
MCD10 (VG6) (VP9)
MCD11(VG7) (VP10)
MCD12(VR2) (GRDY)
MCD13(VR3) (VP11)
MCD14(VR4) (VP12)
MCD15 (VR5) (VP13)Memory data bus for DRAM C (Frame Buffer).  When a frame
buffer DRAM is not required, this bus may be used to input up
to 18 bits of RGB data from an external PC-Video subsystem
or 16 bits of RGB from an external VAFC interface.  Note that
this configuration also provides additional panel outputs so
that a video input port may be implemented along with a 24-
bit true-color TFT panel (TFT panels never need DRAMC).  In
VAFC interface mode, pin 106 is the VAFC Enable Video
Input.  The external VAFC interface drives this pin low to
indicate data input on the VP0-15.  EVID# is ignored
(essentially reserved) in the 65550 (VAFC data is always
expected as inputs).  In VAFC mode, pin 119 is Graphics
System Ready out and is always driven high. 
						

							2-52Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionFlat Panel Display Interface71
72
73
74
75
76
78
79
81
82
83
84
85
86
87
88P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit
panel interfaces may also be supported (see CA0-7 for P16-
23).
Refer to Table 2-7 for the configurations for various panel
types.70SHFCLKOutShift Clock.  Pixel clock for flat panel data.67FLMOutFirst Line Marker.  Flat Panel equivalent of VSYNC.68LPOutLatch Pulse.  Flat Panel equivalent of HSYNC.69M (DE) (BLANK#)OutM signal for panel AC drive control. (may also be called
ACDCLK). May also be configured as BLANK# or as Display
Enable (DE) for TFT Panels.62
61ENAVDD
ENAVEE (ENABKL)I/O
I/OPower sequencing controls. Power sequencing controls. for
panel driver electronics voltage VDD and panel LCD bias
voltage VEE53ACTII/OActivity Indicator.  May be configured for other functions54ENBKLI/OEnable Backlight Outputs.  May be configured for other
functionsFlat Panel Display Interface65HYSNC (CSYNC)OutCRT Horizontal Sync (polarity is programmable) or
Composite Sync for support of various external NTSC / PAL
encoder chips.
Note CSYNC can be set to output on the ACTI or ENABKL
pins.64VSYNC (VISINT)OutCRT Vertical Sync (polarity is programmable) or Vsync
Interval for support of various external NTSC / PAL encoder
chips.60
58
57RED
GREEN
BLUEOutCRT analog video outputs from the internal color palette
DAC.  The DAC is designed for a 37.5 W equivalent load on
each pin (e.g. 75 W resistor on the board, in parallel with the
75 W CRT load. 
						

							Major Chips Description2-53Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionFlat Panel Display Interface (continued)55RSETInSet point resistor for the internal color palette DAC.  A 560 W
1% resistor is required between RSET and AGND.59
56AVCC
AGNDVCC
GNDAnalog power and ground pins for noise isolation for the
internal color palette DAC.  AVCC should be isolated from
digital VCC as described in the Functional Description of the
internal color palette DAC.  For proper DAC operation, AVCC
should not be greater than IVCC.  AGND should be common
with digital ground but must be tightly decoupled to AVCC.
See the Functional Description of the internal color palette
DAC for further information .203XTALI (MCLK)InCrystal In.  This pin .serves as the input for an external
reference oscillator (usually 14.31818 MHz). Note that in test
mode for the internal clock synthesizer, MCLK is output on
A25 (pin 30) and VCLK is output on A24 (pin204(Reserved)Reserved.  For compatibility with the 65545, this pin (formerly
Crystal Out or XTLAO) must be disconnected.  In addition,
pin 150 must be pulled down on reset.  The 65545 no longer
supports the internal oscillator option.205
202
206
208CVCC0
CGND0
CVCCI
CGNDIVCC
GND
VCC
GNDAnalog power and ground pins for noise isolation for the
internal clock synthesizer.  Must be the same as VCC for
internal logic.  VCC/GND pair 0 and VCC/GND pair 1 pins
must be carefully decoupled individually.
Note that the CVCC voltage must be the same as the voltage
for the internal logic (IVCC).15432KHz (GP102) (AA9)InClock input for refresh of non-self-refresh DRAMs and panel
power sequencing.  This pin can be programmed as GP102
instead of 32KHz input, or AA9 for 512Kx3 memory
configurations.Power / Ground and Standby Control178STNDBY#INStandby Control Pin.  Pull this pin to place the chip in
Standby Mode.80
77
181
184IVCC
IGND
IVCC
IGNDVCC
GND
VCC
GNDPower / Ground  (Internal Logic).  5V±10% or 3.3V±0.3V.
Note that this voltage must be the same as CVCC (voltage for
internal clock synthesizer).  This voltage must also be equal
to, or greater than AVCC (voltage for DAC).9
12
26
42
39
52BVCC
BGND
BGND
BVCC
BGND
BGNDVCC
GND
GND
VCC
GND
GNDPower / Ground (Bus Interface) 5V±10% or 3.3V±0.3V.