Acer Extensa 610 Service Guide
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2-64Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)TERMINALNAME NO.I/OTYPEFUNCTIONPCI Address and Data TerminalsC/BE3 180 C/BE2 192 C/BE1 203 C/BE0 5I/O8us commands and byte enables. These are muitiplexed on the same PCI terminals. During the address phase, C/BE-0 define the bus command. During the data phase, C /ENEW-O are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD7-0), C/BE1 applies to byte 1 (AD15-8), C/BE2 applies to byte 2 (AD23-16),and C/BE3 applies to byte 3 (AD31-24).PAR 202I/OParity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI 1131 calculates even parity across the AD and C/BE buses and outputs the results on PAR, delayed by one clock.PCI Interface Control TerminalsDEVSEL 197I/ODevice select. As a PCI target, the PCI1131 asserts DEVSEL to claim the current cycle. As a PCI master, the PCI1131 monitors this signal until a target responds or a time out occurs.FFAME 193Cycle frame. Driven by the current master to indicate the beginning and duration of an access, FRAME I/O is low (asserted) to indicate that a bus transaction is beginning. While FFGI9IE is asserted, data transfers continue. When FRAME is sampled high (deasserted), the transaction is in the final data phase .GNT 168IGrant. Driven by the PCI arbiter to grant the PCI1131 access to the PCI bus after the current data transaction has completed.IDSEL 182IInitialization device select. IDSEL selects the PCI1t31 during configuration accesses. IDSEL can be connected to one of the upper 24 PCI address lines.IRDY 195I/OInitiator ready. IRDY indicates the bus masters ability to complete the current data phase of the transaction. IRDY is used in conjunction with IRDY. A data phase is completed on any clock where I/O both IRDY and TRDY are sampled low (asserted). During a write, IRDY indicates that valid data is present on AD31-0. During a read, IRDY indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are low (asserted) at the same time. This signal is an output when the PCI1131 is the PCI bos master and an input when the PCI bus target.STOP 198I/OStop. This signal is driven by the current PCI target to request the master to stop the current transaction.PERR 99I/OParity error. This signal is driven by the PCI target during a write to indicate that a data parity error has . been detected.REQ 169ORequest. Asserted by the PCI1131 to request access to the PCI bus as a master.SERR 200OO System error. Output pulsed from the PCI1131 indicating an address parity error has occurred.
Major Chips Description2-65Table 2-13PCI1131 Pin Descriptions (Continued)TERMINALNAME NO.I/OTYPEFUNCTIONPCI Interface Control TerminalsTRDY 196I/OTarget ready. Indicates the PCI 1131 ability to complete the current data phase of the transaction. TRDY is used in conjunction with IRDY. A data phase is completed on any clock where both TRDY I/O are sampled asserted. During a read, TRDY indicates that valid data is present on AD31-0. During a write, TRDY indicates the PCI1131 is prepared to accept data. Wait cycles are inserted until both TIRDY and TRDY are asserted together. This signal is an output when the PCI 1131 is the PCI target. and an input when it is the PCI bus master.IRQ10/CLKRUN 159 IRQ12/CLKRUN 161I/OInterrupt Request 10 and 12. This terminal is software configurable and is used by the PCI 1131 to support the PCI Clock Run protocol. When configured as CLKRUN, by setting bit 0 in the System Control Register at offset 80h, this terminal is an open drain output. To select between IRQ10 and IRQ12 as the output use bit 7 of Register 80h.TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹1 6-bit PC Card Address and Data (Slots A and B)A25 121 55 A24118 53 A23116 51 A22114 49 A21111 47 A20109 45 A19107 42 A18105 40 A17103 37 A16112 48 A15115 50 A14108 43 A12106 41 A11100 34 A1095 29 A9102 36 A8104 39 A7119 54 A6123 57 A5125 59 A4126 60 A3128 62 A2131 65 A 1132 66 A0133 67OPC Card Address. 16-bit PC Card address lines. A25 is the most significant bit.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
2-66Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹1 6-bit PC Card Address and Data (Slots A and B)D1593 27 D1491 25 D1389 23 D1287 20 D1184 18 D10147 81 D9145 79 D8142 77 D690 24 D588 21 D485 19 D383 17 D2146 80 D1144 78 D0141 76I/OPC Card Data. 16-bit PC Card data lines. D15 is the most significant bit.1 6-bit PC Card Interface Control Signals (Slots A and B)CD182 16 CD2140 74IPC Card Detect 1 and Card Detect 2. CD1 and CD2 are connected to ground internally on the PC Card. When a PC Card is inserted into a socket, these signals are pulled low. The signal status is available by reading the Interface Status RegisterBVD1 (STSCHG/ 138 72 RI)IBattery Voltage Detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the Card Status Change Interrupt Configuration Register for enable bits (Section 8.6). See the Card Status Change Register and the Interface Status Register for the status bits for this signal. Status Change. STSCHG is used to alert the system to a change in the READY, Write Protect, or Battery Voltage Dead condition of a 16-bit I/O PC Card. Ring Indicate. RI is used by 1 6-bit modem cards to indicate ring detection.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
Major Chips Description2-67Table 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹1 6-bit PC Card Interface Control Signals (Slots A and B)BVD2137 71 (SPKR)IBattery Voltage Detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD 1 as an indication of the condition of the batteries on a memory PC Card. Both BVD 1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the Card Status Change Interrupt Configuration Register for enable bits. See the Card Status Change Register and the Interface Status Register for the status bits for this signal Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit l /O interface. The audio signals from cards A and B can be combined by the PCI 1131 and output on SPKROUT. (DMA Request) This pin may be used as the DMA request signal during DMA operations to a 16-bit PC Card which supports DMA. If used, the PC Card asserts this signal to indicate a request for a DMA operation.REG130 63OAttribute Memory Select. REG remains high for all common memory accesses. When NES is asserted, access is limited to attribute memory (OE or WE active) and to the l /O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. (DMA Acknowledge) This pin is used as a DACK during DMA operations to a 1 6-bit PC Card which supports DMA. The PCI 1131 asserts this signal to indicate a DMA operation. This signal is used in conjunction with the DMA Read (IOWR) or DMA Write (IORD) strobes to transfer data.RESET 124 58OPC Card Reset. RESET forces a hard reset to a 16-bit PC Card.VS1 134 68 VS2 122 56I/OVoltage Sense 1 and Voltage Sense 2. VS1 and VS2, when used in conjunction with each other, to determine the operating voltage of the 16-bit PC Card.INPACK127 61IInput Acknowledge. This signal is asserted by the PC Card when it can respond to an l/O read cycle at the current address. (DMA Request) This pin may be used as the DMA request signal during DMA operations to a 16-bitPC Card which supports DMA. If used, the PC Card asserts this signal to indicate a request for a DMA operation.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
2-68Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹1 6-bit PC Card Address and Data (Slots A and B)IORD99 33OI/O Read. LORD is asserted by the PCI1131 to enable 16-bit l/O PC Card data output during host I/O read cycles. (DMA Write) This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card which supports DMA. The PCI 1131 asserts this signal during DMA transfers from the PC Card to host memory.IOWR101 35OI/O Write. IOWR is driven low by the PCI1131 to strobe write data into 16-bit l/O PC Cards during host I/O write cycles. (DMA Read) This pin is used as the DMA read strobe during DMA operations to a 16-bit PC Card which supports DMA. The PCI 1131 asserts this signal during DMA transfers from host memory to the PC Card.OE98 32OOutput Enable. OE is driven low by the PCI 1131 to enable 16-bit Memory PC Card data output during host memory read cycles. (DMA Terminal Count) This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PCI 1131 asserts this signal to indicate Terminal Count for a DMA write operation .WAIT136 70IBus Cycle Wait. WET is driven by a 16-bit PC Card to delay the completion of (i e. extend) the memory or l/O cycle that is in progress.WE110 46OWrite Enable . WE is used to strobe memory write data into 16-bit Memory PC Cards. VVE is also used for memory PC Cards that employ programmable memory technologies. (DMA Terminal Count) This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PCI 1131 asserts this signal to indicate Terminal Count for a DMA read operation.READY135 69 (IREQ)IReady . The ready function is provided by the READY signal when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit Memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit Memory PC Card is ready to accept a new data transfer. Interrupt Request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
Major Chips Description2-69Table 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹1 6-bit PC Card Interface Control Signals (Slots A and B)WP139 73 (IOIS16)IWrite Protect. This signal applies to 16-bit Memory PC Cards. WP reflects the status of the write-protect switch on 16-bitmemory PC Cards. For 16-bit l/O cards, WP is used for the 16-bit port ( IOIS16) function. The status of the signal can be read from the interface status register. (I/O is 16 bits). This signal applies to 16-bit l/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I /O port that is addressed is capable of 16-bit accesses. (DMA Request). This pin may be used as the DMA Request signal during DMA operations to a 16-bit PC Card which supports DMA. If used, the PC Card asserts this signal to indicate a request for a DMA operation.CE194 28 CE297 30OCard Enable 1 and Card Enable 2. These signals enable even and odd numbered address bytes. CE1 enables even numbered address bytes, and CE2 enables odd numbered address bytes.CardBus PC Card Address and Data Signals (Slots A and B)CAD31147 81 CAD30145 79 CAD29144 78 CAD28142 77 CAD27141 76 CAD26133 67 CAD25132 66 CAD24131 65 CAD23128 62 CAD22126 60 CAD21123 57 CAD19121 55 CAD18119 54 CAD17118 53 CAD16103 37 CAD15101 35 CAD14102 36 CAD1399 33 CAD12100 34 CAD1198 32 CAD1097 30 CAD995 29 CAD893 27 CAD792 26 CAD689 23 CAD590 24 CAD487 20 CAD388 21 CAD284 18 CAD185 19 CAD083 17I/OCardBus PC Card address and data These pins are multiplexed address and data signals A bus transaction consists of an address phase followed by one or more data phases The PCI 1131 supports both read and write bursts. The address phase is the clock cycle in which CFRAME is asserted. During the address phase, CAD31-0 contain a physical address (32- bits). For l/O, this is a byte address; for configuration and I/O memory, it is a DWORD address. During data phases, CAD74 contain the least significant byte and CAD31-24 contain the most significant byte. Write data is stable and valid when is asserted. Read data is stable and valid when CTRDY is asserted. Data is transferred during those clocks when CIRDY and CTRDY are asserted. Note: + Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
2-70Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹CardBus PC Card Address and Data Signals (Slots A and B)CC/BE0 94 28 CC/BE1104 39 CC/BE2117 52 CC/BE3130 63I/OCardBus PC Card Command and Byte Enables. These signals are multiplexed on the same pin. During the address phase of the transaction, CC/BE3 0 define the bus command. During the data I/O phase transaction, CC/BE3-0 are used as Byte Enables. Byte Enables are valid during the entire data phase and determine the byte lanes that will carry the data. CC/BE0 applies to byte 0, CC/BE3 applies to byte 1, CC/EE2 applies to byte 2, and CC/BE3 applies to byte 3.CPAR106 41I/OCardBus PC Card Parity. Even parity across CAD3 1-0 and CC/ES3-O is calculated and driven by this signal. CPAR is stable and valid for one clock after the address phase. For Data phases, CPAR is stable and valid one clock after either CIRDY is asserted on a write transaction or CTRDY is asserted on a read transaction. Once CPAR is valid, it remains valid for one clock after the completion of the current data phase. Note: CPAR has the same timing as CAD31-0 but delays by one clock. When the PCI 1131 is acting as an initiator, it will drive CPAR for address and write data phases; and when acting as a target, the PCI1131 will drive CPAR for read data phases.CardBus PC Card Interface System Signals (Slots A and B)CCLK112 48OCardBus PC Card Clock. This signal provides synchronous timing for all transactions on the CardBus PC Card interface. All signals except MST (upon assertion) CCLKRUN, CIST, CSTSCHG, CAUDIO, CCD2-1, and CVS2-1 are sampled on the rising edge of the clock, and all timing parameters are defined with the rising edge of this signal. The CardBus clock operates at 33 MHz, but it can be stopped in the low state.CCLKRUN 139 73I/OCardBus PC Card Clock Run. This signal is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI 1131 to indicate that the CCLK frequency will be decreased.CRST124 58OCardBus PC Card Reset. This signal is used to bring CardBus PC Card specific registers, sequencers, and signals to a consistent state. When ZMT is asserted, all CardBus PC Card signals must be driven to high impedance state, but the PCI 1131 will drive these signals to a valid logic level. Assertion may be asynchronous for the CCLK but deassertion must be synchronous to the CCLK.CardBus PC Card Interface Control Signals (Slots A and B)CCD182 16 CCD2140 74ICardBus Detect 1 and CardBus Detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to determine the type and voltage of the CardBus PC Card. The signal status is available by reading the Interface Status Register+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
Major Chips Description2-71Table 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹CardBus PC Card Interface Control Signals (Slots A and B)CBLOCK 107 42I/OCardBus Lock. This is an optional signal used to lock a particular address, ensuring a bus initiator exclusive access. NOTE: This signal is not supported on the PCI 1131.CDEVSEL 111 47I/OCardBus Device Select. When actively driven, this signal indicates that the PCI 1131 has decoded its address as the target of the current access. As an input, CDEVSEL indicates whether any device on the bus has been selected.CDEVSEL 109 45I/OCardBus Stop. This signal indicates the current target is requesting the initiator to stop the current transaction.CSTSCHG 138 72ICardBus Status Change. CSTSCHG is used to alert the system to a change in the READY, WP, or BVD condition of the l/O CardBus PC Card.CAUDIO 137 71ICardBus Audio. This signal is an optional digital input signal from a PC Card to the systems speaker. CardBus cards support two types of audio: single amplitude, binary waveform, and/or Pulse Width Modulation (PWM) encoded signal. The PCI1131 supports the Binary Audio Mode, and may output a binary audio signal from the PC Card to the SPKROUT signal.CIRDY115 50I/OCardBus Initiator Ready. This signal indicates that the PCI1131 is initiating the bus initiator ability to complete a current data phase of the transaction. It is used in conjunction with CTRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a write, CIRDY indicates that valid data is present on CAD31-0, and during a read, it indicates the PCI 1131, as an initiator, is prepared to accept the data. Wait cycles are inserted until both CTRDY and CFRDY are both low (asserted).CTRDY114 49I/OCardBusTargetReady. This signal indicates that the PCI 1131, as a selected targets has the ability to complete a current data phase of the transaction. It is used in conjunction with CIRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a read, CTRDY indicates that valid data is present on CAD31-0, and during a write, it indicates the PCI 1131, as a target, is prepared to accept the data. Wait cycles are inserted until both CIRDY and CTRDY are both low (asserted).CFRAME 116 51I/OCardBus Cycle Frame. This signal is driven by the PCI 1131 when it is acting as an initiator to indicate the beginning and duration of a transaction. CFRAME is asserted to indicated a bus transaction is beginning, and while it is asserted, data transfer is continuous. When CFRAME is high (deasserted), the transaction is in its final data phase.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
2-72Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)TERMINALName SlotSlotI/OTYPEFUNCTION A+ B¹ ¹CardBus PC Card Interface Control Signals (Slots A and B)CREQ127 61ICardBus Request. This signal ir1dicates to the arbiter that the CardBus PC Card desires use the CardBus bus.CGNT110 46OCardBus Grant. This signal is driven by the PCI 1131 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has completedCPERR108 43I/OCardBus Parity Error. This signal reports errors during all CardBus PC Card transactions except during special cycles. This signal is sustained in a high-impedance state and must be driven active by the agent receiving data, two clocks following the data, when a data parity error is detected. This signal must be driven active for a minimum duration is one clock for each data phase. CPERR must be driven high for one clock before it is returned to the high-impedance state. An agent cannot report a CPERR until it has claimed the access by asserting CDSVSEL and completed a data phase.CSERR136 70ICardBus System Error. This signal reports address parity error, data errors on the Special Cycle command, or any other system error where the result could be catastrophic, such that the CardBus card may no longer operate correctly. CSERR is open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error. The assertion of this signal is synchronous to the Cock and meets the setup and hold times of all bussed signals. Restoring of the CSERR to the deasserted states is accomplished by a weak pull-up which is provided by the system designer. This pull-up may take two to three clock periods to fully restore ~R The PCI1131 reports CSERR to the operating system anytime it is sampled low (asserted)CVS1134 68 CVS2122 56I/OCardBus Voltage Sense 1 and Voltage Sense 2. CVS1 and CVS2, are used in conjunction with each other, along with CCD1 and CCD2, to determine the operating voltage of the CardBus PC Card.CINT135 69ICardBus Interrupt. This signal is asserted low by a CardBus PC Card to request interrupt servicing from the host.+ Terminal name is preceded with A_. As an example, the full name for terminal 121 is A_A25. ¹ Terminal name is preceded with B_. As an example, the full name for terminal 55 is B_A25.
Major Chips Description2-73Table 2-13PCI1131 Pin Descriptions (Continued) TERMINALNAME NOI /O TYPEFUNCTIONInterrupt TerminalsIRQ3/INTA 154 IRQ4/INTB 155OInterrupt Request 3 and Interrupt Request 4. These terminals may be connected to either PCI or ISA interrupts. These terminals are software configurable as IRQ3 or T1VTA, and as IRQ4 or T1~. When configured for IRQ3 and IRQ4, these terminals should be connected to the ISA IRQ programmable interrupt controller. When these pins are configured for INTA and INTB, these terminals should be connected to available interrupts on the PCI bus.IRQ7/ PCDMAREQ 157OInterrupt Request 7. This terminal is software configurable and is used by the PCI1131 to request PC/PCI DMA transfers from chip sets that support the PC/PCI DMA scheme. When this pin is configured for PC/PCI DMA request (IRQ7) it should be connected to the appropriate request (REQ#) pin on the Intel MPIIX controller.IRQ9/ IRQSER 158OInterrupt Request 9. This terminal is software configurable and indicates an interrupt request from one of the PC Cards. When this pin is configured for IRQ9 it should be connected to the IRQ programmable interrupt controller. IRQSER allows all IRQ signals to be serialized onto one pin. This signal is configured in the Device Control Register of the TI Extension Registers.IRQ11/ PCDMAGNT 160OInterrupt Request 11. This terminals software configurable and is used by the PCI 1131 to accept a grant for PC/PCI DMA transfers from chip sets that support the PC/PCI DMA scheme. When this pin is configured for PC/PCI DMA grant (IRQ11) it should be connected to the appropriate grant (GNT#) pin on the Intel MPIIX controller.IRQ10/ CLKRUM 159 IRQ12/ CLKRUM 161I/OInterrupt Request 10 and t2. This terminal is software configurable and is used by the PCI1131 to support the PCI Clock Run protocol. When configured as CLKRUN, by setting bit 0 in the System Control Register at offset 80h (Section 7.27), this terminal is an open drain output. To select between IRQ10 and IRQ12 as the output use bit 7 of Register 80h.IRQ5 156 IRQ14 162OInterrupt Requests 5 and 14. These signals are ISA interrupts. These terminals indicate an interrupt request from one of the PC Cards. The Interrupt mode is selected in the Device Control Register of the TI Extension Registers.