Acer Extensa 610 Service Guide

							Date: February 12, 1997Sheet   24of   25
SizeDocument NumberREV
A396149SC
Title
370P/J (H/W JUMPER SETTING)TAIPEI TAIWAN R.O.C ACER
ALADDIN III
PULL L: 5V suspend mode enable.
PULL H: 5V suspend mode disable.
L: DMA DACK[7:5,3:0] polling enable.
H: DMA DACK[7:5,3:0] polling disable.*** If L, add ALDN3 P.21 MUX!   12
R171
10KR3
    12
R43
10KR3
 
XDIR
SPLED
+5V
4
4
COMMON
 3  41
4
7
U41B
SSHCT04
  1
  21
4
7
U41A
SSHCT04
 
$CPURSTPCIRST#
RSTDRV
+5V
+5V
4 3,10,14,17,21,22
11,13,15
+5V
  9
 10
 8 1
4
7
U17C
SSHC00
 
5VSB_DC
  2
  3
 1 1
4
7
U1XA
SSHC02
 
POWER: VCC_IDE & GND
  1
  2 3 1
4
7U45A
SSHCT32
    4
  5 6 1
4
7
U45B
SSHCT32
 
IOW#RTCROMCS#
IOR#RTCDS
RTCRW
+5V
+5V
4
4 4
9
9
L: Internal keyboard cntrler enable.
H: Internal KBC disable.
L: Internal RTC enable.
H: Internal RTC disable.
L: External I/O APIC mode supported.
H: Ext. I/O APIC mode not supported.
Must pull High.*** Refer to CKT down left.   12R42
10KR3
    12
R20
10KR3
    12
R38
10KR3
 
  12
R173
10KR3
    12
R170
560R3
 
SPKR
PHOLD#
TC
KBCS#
RTCROMCS#
4 4
4
  9 8 1
4
7
U46D
SSHCT04
 
  5 6 1
4
7
U46C
SSHCT04
 +5V
+5V
5VSB_DC
 11
 12
13 1
4
7
U1XD
SSHC02
 
  9 8 1
4
7
U38D
SSHC14
 +5V
 1110 1
4
7
U41E
SSHCT04
 
 13
12 1
4
7
U41F
SSHCT04
 
+5V
+5V
+5V
 11
10 1
4
7
U46E
SSHCT04
 
  1
 2 1
4
7
U46A
SSHCT04
 +5V
 12
 1311 1
4
7U45D
SSHCT32
 
  1
  2 3 1
4
7
U44A
SSHCT32
 
A_CD1#A_CD2#
B_CD1#B_CD2#
+5V
+5V
22 22
22 22
 12
 1311 1
4
7
U17D
SSHC00
 
EXCACD#
+5V
8 
						

							Date:  January 27, 1997Sheet   25of   25
SizeDocument NumberREV
A396149SC
Title
370P/J (BYPASS CAPACITORS)TAIPEI TAIWAN R.O.C ACER
C240
SCD1U
 C213
SCD1U
 C232
SCD1U
 M1521C108
SCD1U
 
3.3V
1
2C122
ST100U10VDK
 C248
SCD1U
 C118
SC10U16V
 
3.3V
C110
SC1U16V5ZY
 
CPU
CLOSE TO PIN7,9,11,13,15,17
BYPASS CAPACITORS
1
2C238
ST100U10VDK
 1
2C246
ST100U10VDK
 C120
SCD1U
 C251
SC2K2P
 
2.9V2.9V
C113
SC1000P50V3KX
 P/N: 80.15711.341
7343,D SIZE
CLOSE TO PIN 269,271,273,275,277,279CLOSE TO PIN88,98,108,118,128,138
CLOSE TO PIN 19,21,23,35,27,29
C106
SCD1U
 1
2C117
ST100U10VDK
 
C119
SCD1U
 C115
SC2K2P
 C127
SCD1U
 
C242
SCD1U
 C249
SCD1U
 
3.3V
3.3V3.3V
2.9V2.9V
C121
SC1000P50V3KX
 C112
SC1000P50V3KX
 
M1523
CLOSE TO PIN 105,106,119
CLOSE TO PIN 201,202
C114
SC2K2P
 
C124
SCD1U
 C123
SCD1U
 
3.3V
CLOSE TO PIN 190,203,204
C239
SCD1U
 C243
SCD1U
 
C245
SCD1U
 
C116
SCD1U
 
3.3V
+5V
3.3V
C111
SC1U16V5ZY
 
C258
SCD1U
 C36
SCD1U
 C247
SCD1U
 C206
SCD1U
 
C219
SCD1U
 C220
SCD1U
 C95
SCD1U
 
C26
SCD1U
 C170
SCD1U
 C273
SCD1U
 
+5VHDD+5V
+5V
CX38
SCD1U
 CX39
SC10U16V
 
HDD+5V
CY1
SC4D7U16V6ZY
 CY2
SCD1U
 CY3
SC1000P50V3KX
 
CLOSE TO PIN 156
CLOSE TO PIN 105
C230
SC4D7U16V6ZY
 
C267
SC4D7U16V6ZY
 C233
SCD1U
 
+5V
HDD+5V
CY4
SC1U16V5ZY
 CLOSE TO PIN 144,153CLOSE TO PIN 120CLOSE TO PIN 200
CLOSE TO PIN 40CLOSE TO PIN 72
C102
SCD1U
 
C256
SCD1U
 
C30
SCD1U
 
3.3V
3.3V
3.3V
+5V
+5V
C98
SC1000P50V3KX
 
C15
SC1000P50V3KX
 
CACHE
CLOSE TO PIN 87,97,107,117,127,137,147CLOSE TO PIN 157,167,177,187,197,207,217
CLOSE TO PIN 113
CLOSE TO PIN 148,158,168,178,198,208
C263
SCD1U
 C236
SCD1U
 C237
SC2K2P
 
3.3V2.9V2.9V2.9V
C235
SC1000P50V3KX
 
C227
SC10U16V
 
+5V
C262
SCD1U
 CLOSE TO PIN 53CLOSE TO PIN 72C109
SCD1U
  
						

							A  p   A  p  p  e  n  d   p  e  n  d  i  x        E i  x        E
BIOS POST CheckpointsBIOS POST CheckpointsE-1This appendix lists the POST checkpoints of the notebook BIOS.
Table E-1POST Checkpoint ListCheckpointDescription04h· Check CPU ID
· Dispatch Shutdown Path
Note:At the beginning of POST, port 64 bit 2 (8042 system flag) is read to
determine whether this POST is caused by a cold or warm boot.  If it is a cold
boot, a complete POST is performed.  If it is a warm boot, the chip initialization
and memory test is eliminated from the POST routine.08h· Reset PIE, AIE, UIE
Note:These interrupts are disabled in order to avoid any incorrect actions from
happening during the POST routine.09h· Initialize m15110Ah· Initialize m15130Bh· Initialize m710110h· DMA(8237) testing & initialization14h· System Timer(8254) testing & initialization18h· DRAM refresh cycle testing
· Set default SS:SP= 0:4001Ch· CMOS shutdown byte test, battery, and check sum
Note:Several parts of the POST routine require the system to be in protected
mode.  When returning to real mode from protected mode, the processor is
reset, therefore POST is re-entered.  In order to prevent re-initialization of the
system, POST reads the shutdown code stored in location 0Fh in CMOS
RAM.  Then it jumps around the initialization procedure to the appropriate
entry point.
The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to
execute POST properly.
· Initialize default CMOS setting if CMOS bad
· Initialize RTC time base
Note:The RTC has an embedded oscillator that generates 32.768 KHz frequency.
To initialize the RTC time base, turn on this oscillator and set a divisor to
32768 so that the RTC can count time correctly1Dh, 1Eh· DRAM type determination 
						

							E-2Service GuideTable E-1POST Checkpoint List (Continued)CheckpointDescription2Ch· 128K base memory testing
· Set default SS:SP= 0:400
Note:The 128K base memory area is tested for POST execution.  The remaining
memory area is tested later.20h· KB controller(8041/8042) testing
· KB type determination
· Write default command byte upon KB type24h· PIC(8259) testing & initialization30h· System Shadow RAM34h· DRAM sizing3Ch· Initialize interrupt vectors4Bh· Identify CPU brand and type35h· PCI pass 040h· Assign I/O if device request41h· Assign Memory if device requested44h· Assign IRQ if device request45h· Enable command byte if device is OK51h· DownLoad keyboard matrix50h· Initialize Video display4Ch· ChipUp initialization for CPU clock checking54h· Process VGA shadow region58h· Set POST screen mode(Graphic or Text)
· Display Acer(or OEM) logo if necessary
· Display Acer copyright message if necessary
· Display BIOS serial number5Ch· Memory testing5Ah· SMRAM test and SMI handler initialization4Eh· Audio initialization60h· External Cache sizing
· External Cache testing(SRAM & Controller)
· Enable internal cache if necessary
· Enable external cache if necessary64h· Reset KB device
· Check KB status
Note:The keyboard LEDs should flash once. 
						

							BIOS POST CheckpointsE-3Table E-1POST Checkpoint List (Continued)CheckpointDescription7Ch· Reset pointing device
· Check pointing device70h· Parallel port testing74h· Serial port testing78h· Math Coprocessor testing80h· Set security status84h· KB device initialization
· Set KB led upon setup requests
Note:If keyboard Number Lock is enabled, the NumLock LED (if present) should be
turned on.
· Enable KB device6Ch· FDD testing & parameter table setup
Note:The FDD LED should flash once and its head should be positioned88h· HDD testing & parameter table setup89h· Get CPU MUX
Note:This routine is to identify the user-set CPU frequency, not CPU-required
frequency90h· Display POST status if necessary
· Change POST mode to default text mode93h· Rehook int1c for quiet boot94h· Initialize expansion ROM
· Shadow I/O ROM if setup requests
· Build up free expansion ROM tableA4h· Initialize security featureA8h· Setup SMI parametersA0h· Initialize Timer counter for DOS useAAh· m1523 modifyACh· Enable NMI
· Enable parity checking
· Set video modeB0h· Power-on password checking
· Display configuration table
· Clear memory buffer used for POST
· Select boot device