Toshiba Estudio 162 Owners Manual

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 7
(4) Reset circuit
This circuit detects ON/OFF of the power source, and controls start/
stop of each circuit. The voltage of 3.3V in the MCU PWB is detected
by the reset IC to generate the reset signal.
When the power voltage reaches the specified level, each circuit is
operated, but stopped before the power voltage falls below the speci-
fied level in order to protect against malfunction of the circuit. The
CPU/Flash ROM is reset by the power reset circuit, and system reset
of ASIC, OA982, FAX, and NIC is generated from the CPU (general-
purpose port output). 254 ram_data6 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
255 ram_data5 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
256 ram_data4 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
257 GND_core Power
258 ram_data3 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
259 ram_data2 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
260 ram_data1 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
261 ram_data0 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
262 GND_AC Power
263 ram_data15 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
264 ram_data14 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
265 VCC_AC Power
266 ram_data13 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
267 ram_data12 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
268 ram_data11 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
269 ram_data10 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
270 ram_data9 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
271 ram_data8 IN/OUT SDRAM SDRAM (Image 
process page 
memory) data bus
272 VCC_core Power
273 ram_dqm1 OUT SDRAM SDRAM (Image 
process page 
memory) DQM signal
274 ram_cke OUT SDRAM SDRAM (Image 
process page 
memory)  CKE signal
275 GND_AC Power
276 ram_clk_out SDRAM SDRAMs clock
277 GND_core Power
278 ram_mad12 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
279 ram_mad11 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
280 ram_mad9 OUT SDRAM SDRAM (Image 
process page 
memory) address bus PIN 
No.Signal Name IN/OUT Connected to Description
281 VCC_core Power
282 ram_mad8 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
283 ram_mad7 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
284 VCC_AC Power
285 ram_mad6 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
286 ram_mad5 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
287 ram_mad4 OUT SDRAM SDRAM (Image 
process page 
memory) address bus
288 GND_AC Power
289 cpudata15 IN/OUT CPU CPU data bus
290 cpudata14 IN/OUT CPU CPU data bus
291 cpudata13 IN/OUT CPU CPU data bus
292 cpudata12 IN/OUT CPU CPU data bus
293 cpudata11 IN/OUT CPU CPU data bus
294 cpudata10 IN/OUT CPU CPU data bus
295 cpudata9 IN/OUT CPU CPU data bus
296 cpudata8 IN/OUT CPU CPU data bus PIN 
No.Signal Name IN/OUT Connected to Description
R18
11kF
21
C22
0.1u1 2C23
OPEN1 2R20
10kF
21
IC4
M51957BFP
NC8
GND 4VCC7 NC 1
IN 2
NC 3
Cd5 OUT6R19
3.3kJ21
VCC3 VCC3
/RESET0 (2-C4)
Reset IC
e-STUDIO162_151.book  7 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 8
(5) Heater lamp control circuit
a. Outline
The heater lamp control circuit detects the heat roller surface tempera-
ture, and converts the temperature into a voltage. The converted volt-
age is inputted to the CPU.The CPU converts the inputted analog voltage into a digital value. The
digital conversion value and the set value of the test command are
compared to control ON/OFF of the heater lamp according to the level,
controlling the heat roller surface temperature to be the fixed level.
[High temperature protection circuit in case of CPU hung up
(uncontrollable)]
For IC22 3Pin (reference voltage), +3.3V is divided by the resistor. The
thermistor terminal voltage is inputted to IC22 2Pin. When, therefore,
the voltage at 2Pin falls below the voltage at 3Pin, IC22 1Pin becomes
H and the HL signal is pulled to the GND level, suppressing genera-
tion of the lighting signal of the heater lamp. (IC22 output 1Pin is nor-
mally Low.)
[When the heat roller surface temperature is lower than the set
level]
a. When the thermistor terminal voltage is higher than the set level,
the output signal HL from ASIC becomes HIGH level.
b. This HL signal becomes the HLOUT signal through IC26, and is
inputted to the photo triac coupler in the power PWB. When, there-
fore, the HL signal is HIGH, the internal triac turns on.
c. When the internal triac turns on, the heater lamp lights up.
[When the heat roller surface temperature is higher than the set
level]
a. When the thermistor terminal voltage falls below the set level, the
output signal HL from ASIC becomes LOW level. 
b. The HL signal becomes LOW, the power PWB photo triac coupler
turns OFF, and the heater lamp turns OFF. [When the thermistor is open]
The voltage at IC22 6Pin becomes higher than the voltage at 5Pin, and
the 7Pin output THOPEN becomes LOW. This is inputted to the CPU
to display the trouble code H2.
(6) Driver circuit (Clutch, solenoid)
Since a load cannot be directly driven by each load signal from the
CPU or the ASIC, each load is driven through the driver IC (transistor
array).
A large drive current (load current) is ordained from a small input cur-
rent (ASIC output current).
When the driver input voltage (base resistor input) is HIGH, the transis-
tor turns ON to flow a current through the load, operating the load.
R68
7.5kF
21
R71
4.3kF
21
D1
MA700 12R67
1MF21
R66
1kF
21
R70
10kF
21
R69
1kJ
21
C111
22000p1 2
C113
0.1u1 2
R81
300J
2 1R82
100J
2 1
C112
0.1u
1 2
R83
1.2kF
21
R85
10kF
21
R84
10kJ
21
C114
22000p1 2
D4
1SS3551 2
R86
240J
21
R87
240J
21
IC22A
KIA393F
3
218 4+
-
C110
0.1u
1 2
IC22B
KIA393F
5
678 4+
-IC24A
KIA358F
3
21
8 4+
-
IC26
KID65503F
1B 1
2B 2
3B 3
4B 4
5B 5
6B 6
7B 7
G 8
NC9 1C16
2C15
3C14
4C13
5C12
6C11
7C10Q2
KRA119S
1
2
3D2
KDS2262 1
3D3
KDS2262 1
3
INT5V12V VCC3
VCC3VCC3
12V VCC312V
12V
12V VCC3
5V
MRPS1
HL LDEN PMCLK
FTH
HLOUT PMCLK_A
MRPS_1
/LDEN MRPS_2FTH
RTH
THOPEN RTH_IN
MRPS2
MRPS3
MRPS_3(11-B2)
(11-B2) (6-A1)
(6-A1)
(6-A1)
(5-E3) (2-D1) (2-C1) (2-D1)
(2-D1) (2-C1) (1-A2)
(10-B3)(1-A3)
(4-A4) (5-B2)
(11-C1)
LOAD
+24V
ASIC/CPU
OUT PUT
LOAD
e-STUDIO162_151.book  8 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 9
(7) Toner motor control circuit
The IC32 is the motor drive IC, which generates pseudo-AC wave-
forms by the pulse signal from the ASIC to drive the toner supply
motor.
(8) Main motor control circuit/ LSU (Polygon motor) 
control circuit
The motors are driven by the MMD (main motor) signal and the PMD
(polygon motor) signal from the ASIC.
The MMD signal and the PMD signal are turned HIGH and sentthrough the driver IC27 to the control circuit in the main motor/LSU,
rotating each motor.
When the motor RPM reaches the specified level, the MMLD signal
(main) and the PMLD signal (LSU) become LOW. The CPU detects it
to start process control.
(9) Mirror motor control circuit, ADF motor control circuit, 
Duplex motor control circuit, Shifter motor control 
circuit.
Stepping motors are employed for the mirror motor, the ADF motor,
and the duplex motor. The driver for IC29 (for the mirror motor) is the
bipolar drive constant current drive IC. The drive for IC31 (for the ADF)
is the uni-polar drive constant current drive IC. The drive for IC28 (for
the duplex) and IC30 (for the shifter) is the constant current drive IC.  
Each motor is driven in W1-2 phase excitement, 1-2 phase excitement,
or 2-phase excitement. 
The mirror motor/ADF motor related to image scan are driven by a con-
stant current, and each motor current is switched in each magnification
ratio.
R113
47kJ
21
R112
47kJ
21
C128
10u/35V1 2+
R105
1kJ
2 1
R106
1kJ2 1
IC32
BA6920FP
Vcc17
GND8 Rin 20
Fin 18OUT19
OUT25 VM16
VREF 21
RNF6 PSAVE 19
NC 1
NC 2
NC 3
NC 4
NC 7
NC 10
NC 11
NC 12
NC 13
NC14 NC15 NC22 NC23 NC24 NC25 FINFINC129
0.1u/50V
1 2
24V
PGND
PGND
PGND (TM)
(TM_)TMB_O
TMA_O (4-D3)
(4-D3)(11-A1)
(11-A1)Tonner Motor Driver
IC27
KID65503F
1B 1
2B 2
3B 3
4B 4
5B 5
6B 6
7B 7
G 8
NC9 1C16
2C15
3C14
4C13
5C12
6C11
7C10Q3
KRC106S
1
23 R88
10kJ21
5V
PMD MM_Y2MMD
MM_Y1
MM_Y3
/PMD MMref1 /MMD
MMref2 MMref0
POFF /POFF
/LENDSHOLD (10-B4)
(11-B2)(11-B2) (11-A4)
(6-A3) (6-A3) (6-A3) (2-C1)
(2-C1)
(2-C1) (2-A3)
(2-C1) (2-A3)
(1-D3)
e-STUDIO162_151.book  9 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 10
C116
820p 12
C117
820p
1 2C118
820p1 2
C121
0.1u1 2
C115
820p12
C119
0.1u
1 2
R92
1.5kJ
21
R90
0.68J
1W2 1
R94
30kJ
21
R95
30kJ
21
R91
1.5kJ
21
R89
0.68J
1W2 1
R98
510J
21
R97
1kJ
21
R96
2kJ
21
R93
1kJ
21
IC29
L6219DS or AMM56219
OUT 2A 2
SENSE 2 3
COMP 2 4
OUT 2B 5
GND 6
GND 7
I02 8
I12 9
PHASE 2 10
VREF 2 11
RC 2 12
VSS13 RC 114 VREF 115 PHASE 116 I1117 GND18 GND19 I0120 OUT 1B21 COMP 122 SENSE 123 VS24
OUT 1A 1
5V
24VM 5V
5VPGND
PGND
PGNDPGNDPGND
PGND
PGND
PGND
MM_PH_A OUT_A-
MM_AI0
MM_PH_BMM_BI0
MM_BI1MM_AI1 OUT_A+
OUT_B-
MMref0
MMref1
MMref2 OUT_B+ (10-D2)
(2-A3)
(2-A3)
(2-A3)(2-A3)
(2-A3)
(2-A3)
(5-C1)
(5-C1)
(5-C1)
Scanner Motor Driver
(10-D2)
(10-D2)
(10-D2)
R107
300J
21
C125 2200p
12
R99 7.5kJ2 1
C126 2200p12 R100 7.5kJ
2 1
C132
2200p
1 2
C136
OPEN1 2
C130
OPEN1 2
C127 OPEN
12
C137 OPEN12C135
2200p
1 2
R104 2.4kJ
2 1
R111 2.4kJ2 1R101
1kJ
21
R115
1kJ
21
C134
0.1u1 2R108
620J
21
R109
1.2kJ
21
R110
100J
21
R102
750J
21
R103 1J 2W
2 1IC31
MTD1361/F
CrA 23
CrB 20
VsA 25
RsA 3
VrefA 24
VrefB 19
RsB 12
VsB 18
In /A 26
In A 27
In /B 17
In B 16Vmm22
OUT /A1
OUT A4
OUT /B14
OUT B11
PG15
PG28
R114 1J 2W2 1
PGND
PGND
PGNDPGND
PGND 24VM 5V
SPMT_2
(ADFMT2)SPMT_0
SPMT_3
SPMT_1
MRPS_1
MRPS_2
MRPS_3
(ADFMT0)
(ADFMT3)
(ADFMT1) (5-C2)
(5-C2)
(5-C2)
(4-D3)
(4-D3)
(4-D3)
(4-D3)(11-D1)
(11-D1) (11-E1)
(11-E1)
ADF Motor Driver
D5
MTZ J22B
IC28
TD62064AF
I1 3
NC 4
NC 5
I2 6
NC 10
I3 11
NC 12
NC 13
GND 17O12
O27
O39
O416
COM1
COM8
GND 18I4 14
NC 15
PGND24VDup DMT0/DMT0
DMT1
DMT2
DMT3/DMT1
/DMT2
/DMT3(11-B3)
(11-B3)
(11-B3)
(11-B3) (1-D3)
(1-D3)
(1-D3)
(1-D3)
Duplex Motor Driver
D6
MTZ J22B
IC30
TD62064AFI1 3
NC 4
NC 5
I2 6
NC 10
I3 11
NC 12
NC 13
GND 17O12
O27
O39
O416
COM1
COM8
GND 18I4 14
NC 15 R338
0J2 1
R339
0J2 1
R340
0J2 1
R341
0J2 1
PGND24VSFT SFTMT0
/SFTMT0
SFTMT1
SFTMT2/SFTMT1
/SFTMT2
/SFTMT3
SFTMT3
Shifter Motor Driver
(4-B2)
(4-B2)
(4-B2)
(4-B2)(11-A1)
(11-A1)
(11-A1)
(11-A1)
e-STUDIO162_151.book  10 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 11
(10) OPE PWB
a. Outline
The operation circuit is composed of the LCD control circuit, the key
matrix circuit, the display matrix circuit, and the buzzer circuit, realizing
the U/I functions.  
b. LCD control circuit
The character LCD (COG) in 2 lines and 16 digits is used. The display
data are sent from the MCU (CPU) to LCD internal registers, control-
ling the LCD.
c. Key matrix circuit
The SEL signal is sent from the CPU of MCU to the matrix selector IC
(multiplexer) in the operation circuit. The signal detects OFF/ON of the
key, and is sent to the CPU as serial data. 
d. LED matrix circuit
The display is controlled by inputting the serial data signal, the clock
signal, and the latch signal from ASIC to the LED driver in the opera-
tion circuit.
In the LED driver, data are set to the register (8bit) and latched to con-
trol the IC output port, performing matrix-driving of ON/OFF of the LED.
(11) Carriage Unit
a. Outline
The carriage unit is provided with the CCD PWB, the inverter PWB, the
lamps, etc. A document is radiated, and image data read by the CCD
are A/D converted to be sent to the ASIC. 
b. CCD PWB
The color image sensor uPD8861 (5400 pixels x 3 lines) is used as the
CCD on the CCD PWB to scan images in the resolution of 600dpi/US
letter size in the main scanning direction. 
Image data scanned by the CCD are inputted to AFE (AD9826), where
they are A/D-converted to output digital data. The output digital data
are sent to the MCU PWB and to the ASIC. The ASIC performs image
process with the digital data. 
c. Lamp inverter PWB
The transformer is controlled by the lamp control signal from the MCU
PWB to turn ON/OFF the cool cathode ray tube by the transformer out-
put.
B. DC power circuit
The DC power circuit directly rectifies the AC power and performs
switching-conversion with the DC/DC converter circuit, and rectifies
and smoothes again to generate a DC voltage. 
The constant voltage control circuit is of +5VEN. +24V and +12V are of
the non-control system by winding from the +5VEN winding.  As shown
in fig (1), +24V, +12V, and +5V are provided with the ON/OFF function
by external signals. +3.3V is outputted from +5VEN to the regulator IC. 
Refer to the block diagram, fig (1). 
fig (1) Block diagram
(1) Noise filter circuit
The filter circuit is composed of L and C. It reduces common noises
and normal mode noises generated from the AC line.
The common noise means that generated in each line for GND. Its
noise component is delivered through C002, C003, and C022 to GND. 
The normal noise means that overlapped in the AC line or the output
line. It is attenuated by C023, C001, L002, C004, and L003. Refer to fig
(2).
fig (2) Noise filter circuit
(2) Rush current prevention circuit and rectifying/
smoothing circuit
fig (3) Rush current prevention, rectifying/smoothing circuit
Noise filter
circuit
Rush current
prevention circuit
Rectifying/
smoothing
circuitInverter circuit
(Ringing choke converter system)Rectifying/
smoothing circuit(Semiconductor switch)
Rectifying/
smoothing circuit
+12V regulator IC
(with ON/OFF function)
Overcurrent
protection circuitControl
circuitConstant-voltage
detection circuit
(Semiconductor switch)
+3.3V
regulator IC
e-STUDIO162_151.book  11 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D ELECTRICAL SECTION  13 - 12 Since the AC power is directly rectified, if there were not this rush cur-
rent prevention resistor (TH001), an extremely large rush current
would flow due to a charging current flowing through the smoothing
capacitor C006 when turning on the power. 
To prevent against this, the rush current prevention resistor TH001 is
provided between the rectifying diode D003 and the smoothing diode
C006, suppressing a rush current.
The rectifying/smoothing circuit rectifies a 60Hz AC voltage with the
rectifying circuit, and smoothes it with the smoothing capacitor C006.
(3) Inverter and control circuit (Ringing choke converter 
system)
Fig. (4) Inverter and control circuit
When the power is supplied to this circuit, the DC voltage, Vref, sup-
plied by the rectifying/smoothing circuit is applied through R006 and
R007 to FET (Q001), turning on Q001.
When Q001 is turned on, the drain current, I
D, flows as the waveform B
in Fig. (5) to apply VDC to the main winding, NP, on the primary side.
At the same time, a voltage is generated in N
C winding and applied
through R005 and C008b to the gate of Q001. As a result, Q001 is
turned on rapidly.
At the same time with this, C009 is charged through D001, R001, and
D012. When the potential of C009 reaches 0.7V (= V
BE of Q002), Q002
turns on to turn off Q001.Fig. (5) Ringing choke converter operation waveforms
When Q001 turns off, energy accumulated in the transformer (T001)
flows a current of waveform C in the path indicated with dotted line as
shown in the figure above through D101 and D113 and dissipates to
the secondary output side. When this energy is exhausted, the current
flowing through D101 and D113 turns off. However, the N
S winding has
a slight remaining energy, which generates a voltage in the base wind-
ing N
C and turns on Q001 again to repeat switching operation, supply-
ing a high frequency power to the secondary side.
(4) Overcurrent protection circuit (Primary side)
The ON period extension due to an increased output load is detected,
and the OFF period of Q001 is extended by the control circuit, and
energy accumulated in the primary winding of the transformer T001 is
reduced, providing protection against an overcurrent. Refer to Fig. (4).
(5) Rectifying/smoothing circuit (+5V)
fig (6) Rectifying/smoothing circuit
The high frequency pulse generated by the inverter circuit is
decreased by the converter transformer, rectified by the high frequency
diode D113, and smoothed by C107 and C108. 
fig (7) +5V rectifying/smoothing circuit voltage waveform
IDNp
Ns Nc
Q001
VDS waveform
Q001
ID waveform
Secondary output side
D706 D113
ID waveform
Voltage waveform
Voltage waveform
e-STUDIO162_151.book  12 ページ  ２００４年１２月２日　木曜日　午後９時３７分 
						

							e-STUDIO162/162D/151/151D CIRCUIT DIAGRAM  14 - 1
[14] CIRCUIT DIAGRAM
1. MCU PWB
MCU PWB (CPU section)
C24
0.1u
C4
12p
R11 10kJ
R5
0J
BR20
33J
1
2
3
48
7
6
5
R18
11 k F
C25
47p
R20
10kF
BR21
33J
1
2
3
48
7
6
5
R19
3.3kJ
IC2
HD6412321VF25(H8S/2321)
P35/P34/P33/P32/P31
P30/PD7PD
PD5PD4PDPD2PDPDPEPEPEPEPEPEP
PE
AV c c 103
Vref 104
P40/AN0 105
P41/AN1 106
P42/AN2 107
P43/AN3 108
P44/AN4 109
P45/AN5 11 0
P46/AN6/DA0 111
P47/AN7/DA1 11 2
AV s s 11 3
Vss 11 4
P17/PO15/TIOCB2/TCLKD 11 5
P16/PO14/TIOCA2 11 6
P15/PO13/TIOCB1/TCLKC 11 7
P14/PO12/TIOCA1 11 8
P13/PO11/TIOCD0/TCLKB 11 9
P12/PO10/TIOCC0/TCLKA 120
P11/PO9/TIOCB0/DACK1
121
P10/PO8/TIOCA0/DACK0122
MD0 123
MD1 124
MD2 125
PG0/CAS
126
PG1/CS3127
PG2/CS2128
PG3/CS11
PG4/CS02
Vss 3
NC 4
VCC 5
PC0/A0 6
PC1/A1 7
PC2/A2 8
PC3/A3 9
Vss 10
PC4/A4 11
PC5/A5 12
PC6/A6 13
PC7/A7 14
PB0/A8 15
PB1/A9 16
PB2/A10 17
PB3/A11 18
Vss 19
PB4/A12 20
PB5/A13 21
PB6/A14 22
PB7/A15 23
PA0/A16 24
PA1/A17 25
PA2/A18 26
PA3/A19 27
Vss 28
PA4/A20/IRQ429
PA5/A21/IRQ530
PA6/A22/IRQ631
PA7/A23/IRQ732
P67/
/ CS7 IRQ333
P66/
/ CS6 IRQ234
Vss 35
Vss 36
P65/IRQ137
P64/IRQ038P53/ADTRG
102
P52/SCK2101
Vss100
Vss99
P51/RxD298
P50/TxD297
PF0/BREQ96
PF1/BACK95
PF2/
/WAIT/BREQO LCAS94
PF3/LWR93
PF4/HWR92
PF5/RD91
PF6/AS90
VCC89
PF7/088
Vss87
EXTAL86
XTAL85
VCC84
STBY83
NMI82
RES81
WDT
OVF80
P20/PO0/TIOCA379
P21/PO1/YICOB378
P22/PO2/TIOCC377
P23/PO3/TIOCD376
P24/PO4/TIOCA475
P25/PO5/TIOCB474
P26/PO6/TIOCA573
P27/PO7/TIOCB572
P63/TEND171
P62/DREQ170
P61/ /TEND0 CS569
Vss68
Vss67
P60/
/ DREQ0 CS466
Vss65
R4 *3
BR22
33J
1
2
3
48
7
6
5
C1
*6
R13 10kJ
R2 *2
BR23
33J
1
2
3
48
7
6
5IC4
M51957BFPNC8
GND 4VCC7 NC 1
IN 2
NC 3
Cd5 OUT6BR24
33J
1
2
3
48
7
6
5
R7 *4
C381
22pF
R1
OPEN
C382
OPEN
C383
OPEN
C384
OPEN
X1
HC-49U/S
19.6608MHz
R22
10kJ
R21 33J
C22
0.1u
R8 33J
BR110
33J1 2 3 4
8 7 6 5
IC1
P2010/PLL701-01Xin1
Xout2
FS03
Vss4
SSon 5
MODOUT6SR0 7VDD 8
R12 10kJ
C3 *5
R3 *1
R6
0J
R10 100J
R337
33J
C23
OPEN
C2
0.1u
R9 33J
C386
OPEN
A0A5A2A4A11A19A13A3A8A10A7A12A16A14A18A1A15A17A6A9
CPUCLK(NC)
/TRANSST
ADFMT0
/SCANSP
ADFMT1ADFMT2
/SCANST
ADFMT3
/STBYES_CMD
RD
/ESS_RDY/ESC_RDY
HWR/PRINTST
LW R
ESS_TS
RESETOUT1
NMI/WDT
OVF
/CS0#/CS1#/CS2#/CS3#
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
/PRINTST
/RESET0
/ASIC_RST
/ES_PAGE
MSU_ST1
ADFMT0ADFMT2/MIRCNT
(SIN2)
ADFMT1
/TRANSST
(KEYIN)
PMCLK
RTH
ADFMT3
/SCANSP
PSL
/SCANST
(SIN3)(SIN1)
ESS_TS
/ESC_RDYES_CMD
/HWR/LWR
/ESS_RDY
/RD
SELIN3SELIN2SELIN1
/RESET1
/CS3/CS2/CS1/CS0
Spreading Range :
+/- 1.25%
R4(*3) When IC1 is, mounted NOT mounted
OPEN 0J
R3(*1)OPEN 680J
R7(*4)22J OPEN
R2(*2)0J OPEN
C3(*5)
C1(*6)22pF
22pF15pF
15pF
*R2,R3,C1, and C3 are tentative
(2-D2)
(2-E3)(2-E3)
(2-E3)
(4-C3) (4-C2)
(4-C3)
(4-C3)
(2-D1) (5-B2)
(2-C4) (8-A2)
(13-B2)(4-D4) (4-D4)
(4-C3) (4-D4) (5-E3)
(4-D4)
(8-A1)
Reset IC
(4-C2)
(8-A3) (13-B2) (2-C1)
(4-C2) (3-A2)
(4-A2)
(2-C1)
(4-C2) (3-A2)
(8-A3)
(8-A2)
(8-A2)
(9-B2)
A A
B B
C C
4
3
2
1
14_CIRCUTDIAGRAM.fm  1 ページ  ２００４年１２月２日　木曜日　午後７時７分 
						

							e-STUDIO162/162D/151/151D CIRCUIT DIAGRAM  14 - 2
C9 0.1uC14 0.1u
BR8
10kJ 1
2
3
48
7
6
5
BR10
10kJ 1
2
3
48
7
6
5
BR5
10kJ 1
2
3
48
7
6
5
H8S/2321 P35/SCK164
P34/SCK063
P33/RxD162
P32/RxD061
P31/TxD160
P30/TxD059
VCC58
PD7/D1557
PD6/D1456
PD5/D1355
PD4/D1254
Vss53
PD3/D1152
PD2/D1051
PD1/D950
PD0/D849
PE7/D748
PE6/D647
PE5/D546
PE4/D445
Vss44
PE3/D343
PE2/D242
PE1/D141
PE0/D040
VCC39
/QP64/IRQ038Q
Vss
65
BR7
10kJ 1
2
3
48
7
6
5
BR9
10kJ 1
2
3
48
7
6
5
C6
100p
BR11
10kJ 1 2
3 4
8 7
6 5
R15 1kJ
BR14
33J 1
2
3
48
7
6
5
BR12
10kJ 1 2 3
4
8 7 6
5
BR94
10kJ 1
2
3
48
7
6
5
BR16
33J 1
2
3
487
6
5
BR13
10kJ 1
2
3
48
7
6
5
C7
0.1u
BR18
10kJ 1 2 3 4
8 7 6 5
BR17
33J 1
2
3
48
7
6
5
BR15
10kJ 1 2 3
4
8 7 6
5
C10 0.1u
BR19
33J 1
2
3
48
7
6
5
C11 0.1u
IC3
24WC02E01
E12
E23
VSS4
SDA 5SCL 6WC
7VCC 8
C12 0.1u
C385
OPEN
C13 0.1u
C8
10u/16V+ C5
100p
BR1
10kJ 1
2
3
48
7
6
5
R331
33J
BR2
10kJ 1
2
3
48
7
6
5
L1
ZJSR5101-223
BR3
10kJ 1
2
3
48
7
6
5
R14
10kJ
BR4
10kJ 1
2
3
48
7
6
5
R17
OPEN
R16 1kJ
BR6
10kJ 1
2
3
48
7
6
5
CPUCLK(NC)
ADFMT1
(FW)mt_at_home
LW R
/CS0#/CS2#
CPU_SYNC
/CS1#
SCLTxD1
ADFMT0
/SCANSP
(SPPD)
/TRANSST
CCD_TG
SDA
(PSW)
ADFMT3
ARB_INT
/SCANST
ADFMT2
HWRRD
A20(SPPD)MT_HOMECPU_SYNC
(PSW)CCD_TG
(FW)ARB_INT
POFF
SCL
/CS3#
TXD1
A20
(SIN3)(SIN2)(SIN1)
(KEYIN)
SDA
SCLSDA
DMT3
/WDTOVFD14
/CS4#
POFF
D8
D5
RY/BY
D1D0
DMT0
D1
D15
D7
D11
D3
D0
D12D11
RESETOUT1
D13
D8
D3
/CS4#D10
D4
D7
D5
DMT1
RY/BYD9
DMT2
D6
D2
D9
D14
D6D4
D10
/STBY
/PRINTST
D12
D15
D2
D13
/ESC_RDY/ESS_RDYES_CMDESS_TS
DMT3
DMT0DMT2DMT1
NMI
CPU3.3
CPU3.3
VCC3
VCC3
VCC3VCC3VCC3
A[19..0]
mt_at_home
RY/BY
(PSW)CCD_TGCPU_SYNCARB_INT
D[15..0]
(SPPD)
(FW)
SDA1SCL
POFF
DMT2
LCDDB7LCDDB6
DMT1DMT0
TxD1
LCDRSLCDE
LCDDB5LCDDB4
DMT3
/CS4
BZR
(2-A1) (3-A3)(2-B1)
(4-D4)
(14-C3)
(7-E1) (2-B1)
(2-A4)
(7-E1)(2-A1) (6-D4)
(6-D4)
(6-D4)
(6-D4)
(5-B1) (3-B2)
(14-D3)(13-C2) (3-A1) (4-A2)
(4-A1)
(4-B1) (11-B2) (4-C3)
(4-C1)
(4-C1)
Serial EE-PROM
(4-C1) (4-C1)
(4-C1)
(4-C1)
(13-B2)
(8-A2)
C C
D D
E E
4
3
2
1
1/14
14_CIRCUTDIAGRAM.fm  2 ページ  ２００４年１２月２日　木曜日　午後７時７分 
						

							e-STUDIO162/162D/151/151D CIRCUIT DIAGRAM  14 - 3
A
AB
BC
C 4
3
2
1
(14-D3) (1-D2),(14-D3)
(14-A3)
(14-A4) (14-D3)
(14-A2) (14-A2) (14-D3)
(14-D3) (14-A2)
(14-A2)
(14-A2) (14-A2)
(5-B1) (5-B1)
(6-B3)
(6-B3)
(6-B3)
(6-B3)
(6-B3)
(6-B3) (5-B1)
(3-E2)(3-E3)(3-D2) (3-D2)
(3-D2) (3-D2)
(3-D2)
(3-D2) (3-D2) (3-E1)
(3-E2) (3-E2)
(1-D2)
(1-C1)
(5-B1)(1-A2) (4-C3)
(1-D2) (1-D2)
(1-B3) (1-B3)
(1-B1)(5 B1)
(3-A1)(4-A2) (13-C2)
(3-A3)
(3-A2) (13-B2)
(8-A1)
(4-C1)(1-B1)
(9-B2)(3-B2)
MCU PWB (ASIC section)
RAMDB0 RAMDB1 RAMDB2
RAMDB3 RAMDB4 RAMDB5 RAMDB6 RAMDB7
RAMDB15
RAMDB14
RAMDB13
RAMDB12
RAMDB11
RAMDB10
RAMDB9
RAMDB8
SFCLK48
PFCLKIN
PFCLKOUT MM_BI2
MM_AI0 MM_BI1
MM_AI2 MM_BI0
MM_AI1/INREQ /OUTACK /FAXPRO /PCLPRO
/OUTCS
A8D9
/OU TCS
/PCLPRO
MM_BI2
RAMDB13
D7
RAM_CLK_OUT
AFE_SDI
D4
D2
MEM_INT
MM_AI0
RAMDB14
D8
PFC LKIN/FA XPRO D15
PFCLKOUTD3
D0
A7
A6
A5
CLKSW
RAMDB9
/IN REQ
MM_BI1 MM_BI0
MM_AI2 MM_AI1
D1 D13
D5
JTG_ TDI D12
D11
RAMDB12
A4
A2
A1
/OU TACK A9
A3
RAMDB1
D6
SFCLK48
RAMDB15
D10
PFC LK
SYNC#D14
JTG _TDO
RAMDB2
/ES PRD
RAMDB7
RAMDB6
RAMDB5
RAMDB4
RAMDB3
RAMDB0
RAMDB11
RAMDB10
RAMDB8AFE_DB2 AFE_DB7
AFE_DB0 AFE_DB6
AFE_DB3 AFE_DB4
AFE_DB1 AFE_DB5
AFE_DB7
AFE_DB6
AFE_DB5
AFE_DB4
AFE_DB3
AFE_DB2
AFE_DB1
AFE_DB0
AFE_SDI
JTG _TMS
JTG_TCK
JTG_TDI JTG_TMS JTG_TCK
JTG_TDO
MAD11
MAD8
MAD4MAD1 MAD2
MAD5 MAD6 MAD9 MAD3
MAD0
MAD7 MAD12MAD10
RAM_CLK_OUT
AFE_SENADCLK
CCD_CP
CCD_PHI1CCD_PHI2
CCD_TG
AFE_DB[7..0]
CL
CCD_RS
VSAMP
AFE_SCK
AFE_SDI
BSAMP
MM_Y1
MM_PH_AMM_AI0MM_AI1
MM_PH_BMM_BI0MM_BI1
MM_Y2MM_Y3
BANK1BANK0
/SDCAS/SDRAS/SDCS
DQM0
MAD[12..0]
/SDWDE
SDCKEDQM1
SDCLK
D[15..0]A[19..0]/CS2
MIRCNTCPU_SYNC
/LWR/RD
RAMDB[15..0]
ARB_INTMMD(/ASI C_RST)/LENDVIDEO#
/RESET0
VCC3
VCC3
VCC3
VCC3
C397
0.1u
R351
33J
C69 12p
IC5
HG73C138HFV
ASIC
123486759101112131415161718192021222324252627282930313234353637383940414243444546474849
192191190189188187186185184183182181180179178177176175174
256255254253252251250249248247246245244243242241240239238237236235234233232
217
231230
225
221
226
220219
223
218216215
229228227
224
222214213212211210209208207206205204203202201200199198197195196193194
33
257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296
CPU_DATA7
CPU_DATA6
CPU_DATA5
CPU_DATA4
CPU_DATA1 CPU_DATA3
CPU_DATA2 VCC(AC)
CPU_DATA0
GND(AC)
MIRCNT
/CPUSYNC
MEM_INT
ARB_INT
VCC(CORE)
CPU_AD8
CPU_AD7
CPU_AD6
CPU_AD5
GND(CORE)
RAM_CLK_IN
CPU_AD4
CPU_AD3
CPU_AD2
CPU_AD1
CPU_AD0
/CPUCS
SFCLK48
GND(CORE)
/CPUWR
/CPURD
/RESET
PFCLK
CLKSW
GND(CORE)
PFCLKOUT
PFCLKIN
GND(PLL)
VCC(PLL)
GND(PLL)
VCC(PLL)
TM2_15M
/SYNC
GND(AC)
/VIDEO
/LEND
VCC(AC)VCC(CORE)
/INREQ
/OUTCS
/OUTACK
/ESPRD
/FAXPRD
/PCLPRD
GND(AC)
MDAT15
MDAT14
MDAT13
VCC(CORE)
MDAT12
MDAT11
MDAT10
VCC(AC)
MDAT09
MDAT08
RAM_DATA4 RAM_DATA5 RAM_DATA6 RAM_DATA7 GND(AC) RAM_DQM0 RAM_WDE
VCC(AC) RAM_CAS RAM_RAS RAM_CS RAM_BANKS0 RAM_BANKS1
VCC(CORE) RAM_MAD10 RAM_MAD0
RAM_MAD1 GND(CORE) RAM_MAD2 RAM_MAD3 GND(AC) MM_AI2 MM_AI1
MM_AI0 MM_PH_A
AFE_DB3
MM_BI2 MM_BI1 MM_Y2
VCC(AC)
MM_Y1
AFE_DB0
AFE_DB1GND(CORE)AFE_DB2
AFE_DB4
AFE_DB5
MM_BI0 MM_PH_B VCC(CORE) MM_Y3
CLPWM
AFE_DB6
AFE_DB7
GND(AC)
AFESCK
VCC(CORE)
ADCLK
GND(CORE)
AFE_SEN
CCD_PH1
CCD_PH2
AFE_SDI
CCD_CP
BSAMP
CCD_RS
CCD_TG
VSAMP
GND(CORE)
TD0
TRSKTDI
TCK TMS
VCC(CORE)
GND(CORE)
RAM_DATA3
RAM_DATA2
RAM_DATA1
RAM_DATA0
GND(AC)
RAM_DATA15
RAM_DATA14
VCC(CORE)
RAM_DATA13
RAM_DATA12
RAM_DATA11
RAM_DATA10
RAM_DATA9
RAM_DATA8
VCC(CORE)
RAM_DQM1
RAM_CKE
GND(AC)
RAM_CLK_OUT
GND(CORE)
RAM_MAD12
RAM_MAD11
RAM_MAD9
VCC(CORE)
RAM_MAD8
RAM_MAD7
VCC(AC)
RAM_MAD6
RAM_MAD5
RAM_MAD4
GND(AC)
CPUDATA15
CPUDATA14
CPUDATA13
CPUDATA12
CPUDATA11
CPUDATA10
CPUDATA9
CPUDATA8
C67
0.1u
BR60 82J
1234
8765
BR9
1234
R45 0J
R24 33J
BR43 33J
1234
8765
L3
ZJSR5101-223
BR48 10kJ1234
8765
BR2
1234
BR27
33J1234
8765BR30
33J1234
8765
C70 12p
R23 33J
BR61 10kJ1234
8765
C47
47p
R34 10kJ
X2
OSC-31
48MHz
1
85
4
N.C. VCC OUTPUT
GND
R25 33J
R32 10kJ
BR29 10kJ
1234
8765
BR39 33J
1234
8765
C49
47p
BR31 10kJ
1234
8765
BR57 10kJ1234
8765R27 33J
C68
12p
C51
47p
BR53 10kJ1234
8765
BR62 33J
1234
8765 R26 33J
BR63 33J
1234
8765
C50
47p
R29 33J
C52
47pC48
47p
C66
22000p
R30 33J
BR41 33J
1234
8765
C53
47p
BR45 33J
1234
8765
BR33 10kJ1234
8765 R31 33J
X3 HC-49U/S (16.1511MHz)
BR49 33J
1234
8765
C54
47p
BR52 33J
1234
8765
R44 0J
R43
33J
BR56 33J
1234
8765
R33 10kJ
14_CIRCUTDIAGRAM.fm  3 ページ  ２００４年１２月２日　木曜日　午後７時７分 
						

							e-STUDIO162/162D/151/151D CIRCUIT DIAGRAM  14 - 4
C
CD
DE
E4
3
2
1
(1-B3)
(1-A2) (1-A2)
(12-A3)
(4-C3) (4-C3)
(4-C3)
(4-C2)
(4-C2)
(4-D4)
(5-B1)
(5-B1)
(5-B1)
(5-B4)
(5-B4)
(5-B4)
(5-B3)
(5-B3)
(5-B2)
(5-B2)
(5-B2)
(5-B2)
(5-B3)
(5-B3) (5-B3)
(5-B2) (5-B3) (4-C2) (4-C2)
(4-C1)(4-A1)
(4-C2) (4-C2) (4-C2)(8-A2) (4-C3)(12-A3)(8-A2) (8-A2) (8-A2)
(8-A4) (8-A2) (8-A4) (8-A4) (8-A2) (8-A2) (8-A4)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(12-A3)
(5-B4)
(5-B3)
(9-B2)
2/14
PIDATA4 PIDATA0
PIDATA5
PIDATA6 PIDATA1
PIDATA7 PIDATA2
PIDATA3
/REV
/INIT
/SLCTIN
/AUTOF D
/STB /ACK
BUSY
PE /FAULT
SLCTPARAD1
PARAD2
PARAD6
PARAD7 PARAD4 PARAD3
PARAD5 PARAD0
/INIT
/SLCTIN
/AUTOF D
/STB PARAD7 PARAD6 PARAD5 PARAD4 PARAD3 PARAD2 PARAD1 PARAD0 VPIN RCV
VMIN /POREQ
/PIREQ
PODATA0
PODATA1
PODATA2
PODATA3
PODATA4
PODATA5
PODATA6
PODATA7 CLKSW MEM_INT PODATA 5
PODATA 7
PFCLK
SYNC# PODATA 3 PODATA 1
PODATA 2
PODATA 4
PODATA 6 PODATA 0
RCV
VPI N
VMI N
/H_SYNC
PIDATA[7..0]
PODATA[7..0]/POACK/PIREQ
/PORE Q
/PIACK/PIW R
/SCANSP
/SCANST
/TRANSST/PRINTS T
/REV
/INIT
/ACKBUSYPE
/FAULT
SLCT
/SLCTI N/ST B
PARAD[7..0]
/AUTOF D
OP_CLK
TMTM_
OP_LATCHOP_DATA
(/SYNC)
CPFS2PRHLMPFSMIRONADFONKEYSC1KEYSC3KEYSC2
SPUSSPFSVF MMRPS1MCPMDCPFS1DEVDIRMRPS3VFMCNTLDENGRID LMMDRRSSRRCMRPS2BI ASTC/LENDVIDEO#
/PR_LINE/SC_LINE
/IMC_READY
/FPOFFSGS
/OA_RST
(/ASIC_RST)
/RESET 1
/FWREN
G3.3V
VCC3VCC3VCC3
VCC3
VCC3
VCC3
G3.3V
VCC3
VCC3
VCC3R352 33J
C33 0.1 u
R41
10kJ
C27 0.1 uC34 0.1 uC35 0.1 u
464748495152535455575658596061626364
86848381
69
8079
72
787776
686766657473
82
71
75
85
70
96
92
8788899091939495979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128
177176175174173172171170169168167166165164163162161160159158157156155154153152151150149
148147146145144143142141140139138137136135134133132131130129
50/VIDEO/LEND
VCC(AC)
OUTP00A
OUTP02A
OUTP03A
OUTP04A
OUTP05A
OUTP06A
VCC(CORE) OUTP15A
OUTP07A
OUTP08A
GND(CORE)
OUTP09A
OUTP10A
OUTP11A
OUTP12A
VCC(CORE)
OUTP13B
OUTP12B
OUTP10B
GND(AC)
OUTP09B
OUTP08B
OUTP03B
GND(CORE)
OUTP07B
OUTP06B
OUTP00B OUTP14A VCC(CORE) OUTP13A
VCC(AC) OUTP04B
OUTP11B
OUTP02B
OUTP05B OUTP14B
OUTP01B
TSP_MODE
OPE_CLK
/TMTM OPE_DATA OPE_LATCHGND(AC)VCC(AC) /SCANSPTSO0 IE1284_STB IE1284_AUTOFDVCC(CORE) IE1284_SLCTINIE1284_INIT IE1284_SLCTGND(CORE)IE1284_PE IE1284_BUSYIE1284_ACK IE1284_FAULTVCC(CORE) IE1284_REV IE1284_PARAD7
IE1284_PARAD6 IE1284_PARAD5 IE1284_PARAD4 IE1284_PARAD3 IE1284_PARAD2VCC(AC) IE1284_PARAD1 IE1284_PARAD0SUSPENDGND(AC)OEN VMOUTVPOUT GND(CORE)VMINVPINRCV /SCANST
VCC(
AC)
MDAT09
MDAT08
MDAT07
GND(CORE)
MDAT06
MDAT05
MDAT04
VCC(CORE)
MDAT03
MDAT02
MDAT01
MDAT00
GND(AC)
/INCS
/INACK
/OUTREQ
GND(CORE)
/HSYNC
PIDATA0
PIDATA1
PIDATA2
VCC(AC)
PIDATA3
PIDATA4
PIDATA5
PIDATA6
PIDATA7
/POCS/POREQ
VCC(AC)
/PIWT
/PIACK
GND(AC)
/POACK
/PIREQ
GND(CORE)
PODATA0
PODATA1
PODATA2
PODATA3
PODATA4
PODATA5
PODATA6
PODATA7
VCC(CORE)
/TRANSST
/RECEPTST
/PRINTST
OUTP01A
C38 0.1 u
BR93 10KJ
1234
8765
C41 0.1 uC39 0.1 u
C71
47p
C40 0.1 u
BR25 10KJ
1234
8765
BR40 10kJ1234
8765
R354 N.M.
C37 0.1 u
BR37 10kJ1234
8765
R46
10J
BR47 33J
1234
8765
BR26 33J
1234
8765C42 0.1 u
BR35 10kJ1234
8765
R35
10kJ
C43 0.1 uC44 0.1 u
BR59 10kJ1234
8765
BR34 33J
1234
8765
C45 0.1 uC46 0.1 u
BR46 10kJ1234
8765
R40
OPENR42
10kJ
C55 0.1 u
BR50 10kJ1234
8765
BR51 33J
1234
8765
C62 0.1 u
BR54 10kJ1234
8765
R353 N.M.
R28
10KJ
BR44 33J
1234
8765
R355
N.M.
R358
10kJ
C59 0.1 u
BR28 33J
1234
8765
C64 0.1 uC63 0.1 u
+C36
47u/16V
C60 0.1 u
L2
ZJSR5101-102TA
C56 0.1 u
R37
10kJ
BR58 33J
1234
8765
C26 0.1 u
BR32 33J
1234
8765
C58 0.1 u
C30 0.1 u
C57 0.1 u
C28 0.1 u
BR55 33J
1234
8765
C61 0.1 u
R38
OPEN
C29 0.1 u
C65 0.1 u
C31 0.1 u
R310 10J
C398
47p
R39
OPEN
C32 0.1 u
R311 10J
14_CIRCUTDIAGRAM.fm  4 ページ  ２００４年１２月２日　木曜日　午後７時７分