Acer Travelmate 7100 Service Guide

							Major Chips Description2-23Table 2-282371AB Pin DescriptionsNameTypeDescriptionUSBP0+,
USBP0–I/O
SERIAL BUS PORT 0. This signal pair comprises the differential data signal for
USB port 0.
During Reset: High-Z After Reset: High-Z During POS: High-ZUSBP1+,
USBP1–I/O
SERIAL BUS PORT 1. This signal pair comprises the differential data signal for
USB port 1.
During Reset: High-Z After Reset: High-Z During POS: High-ZPOWER MANAGEMENT SIGNALSBATLOW#/
GPI9I
BATTERY LOW. Indicates that battery power is low. PIIX4 can be programmed
to prevent a resume operation when the BATLOW# signal is asserted. If the
Battery Low function is not needed, this pin can be used as a general-purpose
input.CPU_STP#/
GPO17O
CPU CLOCK STOP. Active low control signal to the clock generator used to
disable the CPU clock outputs. If this function is not needed, then this signal can
be used as a general-purpose output.  For values During Reset, After Reset, and
During POS, see the Suspend/Resume and Resume Control Signaling section.EXTSMI#I/OD
EXTERNAL SYSTEM MANAGEMENT INTERRUPT. EXTSMI# is a falling edge
triggered input to PIIX4 indicating that an external device is requesting the
system to enter SMM mode. When enabled, a falling edge on EXTSMI# results
in the assertion of the SMI# signal to the CPU. EXTSMI# is an asynchronous
input to PIIX4.  However, when the setup and hold times are met, it is only
required to be asserted for one PCICLK. Once negated EXTSMI# must remain
negated for at least four PCICLKs to allow the edge detect logic to reset.
EXTSMI# is asserted by PIIX4 in response to SMI# being activated within the
Serial IRQ function. An external pull-up should be placed on this signal.LID/
GPI10I
LID INPUT. This signal can be used to monitor the opening and closing of the
display lid of a notebook computer. It can be used to detect both low to high
transition or a high to low transition and these transitions will generate an SMI#
if enabled. This input contains logic to perform a 16-ms debounce of the input
signal. If the LID function is not needed, this pin can be used as a general-
purpose input.PCIREQ[A:D]#I
PCI REQUEST. Power Management input signals used to monitor PCI Master
Requests for use of the PCI bus. They are connected to the corresponding
REQ[0:3]# signals on the Host Bridge.PCI_STP#/
GPO18O
PCI CLOCK STOP. Active low control signal to the clock generator used to
disable the PCI clock outputs. The PIIX4 free running PCICLK input must remain
on. If this function is not needed, this pin can be used as a general-purpose
output.  For values During Reset, After Reset, and During POS, see the
Suspend/Resume and Resume Control Signaling section.PWRBTN#I
POWER BUTTON. Input used by power management logic to monitor external
system events, most typically a system on/off button or switch. This input
contains logic to perform a 16-ms debounce of the input signal.RI#
GPI12I
RING INDICATE. Input used by power management logic to monitor external
system events, most typically used for wake up from a modem. If this function is
not needed, then this signal can be individually used as a general-purpose input.RSMRST#I
RESUME RESET. This signal resets the internal Suspend Well power plane
logic and portions of the RTC well logic. 
						

							2-24Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionSMBALERT#/
GPI11I
SM BUS ALERT. Input used by System Management Bus logic to generate an
interrupt (IRQ or SMI) or power management resume event when enabled. If this
function is not needed, this pin can be used as a general-purpose input.SMBCLKI/O
SM BUS CLOCK. System Management Bus Clock used to synchronize transfer
of data on SMBus.
During Reset: High-Z After Reset: High-Z During POS: High-ZSMBDATAI/O
SM BUS DATA. Serial data line used to transfer data on SMBus.
During Reset: High-Z After Reset: High-Z During POS: High-ZSUSA#O
SUSPEND PLANE A CONTROL. Control signal asserted during power
management suspend states. SUSA# is primarily used to control the primary
power plane. This signal is asserted during POS, STR, and STD suspend states.
During Reset: Low After Reset: High During POS: LowSUSB#/
GPO15O
SUSPEND PLANE B CONTROL. Control signal asserted during power
management suspend states. SUSB# is primarily used to control the secondary
power plane. This signal is asserted during STR and STD suspend states. If the
power plane control is not needed, this pin can be used as a general-purpose
output.
During Reset: Low After Reset: High During POS: High/GPOSUSC#/
GPO16O
SUSPEND PLANE C CONTROL. Control signal asserted during power
management suspend states, primarily used to control the tertiary power plane.
It is asserted only during STD suspend state. If the power plane control is not
needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: High/GPOSUS_STAT1#/
GPO20O
SUSPEND STATUS 1. This signal is typically connected to the Host-to-PCI
bridge and is used to provide information on host clock status. SUS_STAST1# is
asserted when the system may stop the host clock, such as Stop Clock or during
POS, STR, and STD suspend states. If this function is not needed, this pin can
be used as a general-purpose output.
During Reset: Low After Reset: High During POS: Low/GPOSUS_STAT2#/
GPO21O
SUSPEND STATUS 2. This signal will typically connect to other system
peripherals and is used to provide information on system suspend state. It is
asserted during POS, STR, and STD suspend states. If this function is not
needed, this pin can be used as a general-purpose output.
During Reset: Low After Reset: High During POS: Low/GPOTHRM#/
GPI8I
THERMAL DETECT. Active low signal generated by external hardware to start
the Hardware Clock Throttling mode. If enabled, the external hardware can force
the system to enter into Hardware Clock Throttle mode by asserting THRM#.
This causes PIIX4 to cycle STPCLK# at a preset programmable rate. If this
function is not needed, this pin can be used as a general-purpose input.ZZ/
GPO19O
LOW-POWER MODE FOR L2 CACHE SRAM. This signal is used to power
down a cache’s data SRAMs when the clock logic places the CPU into the Stop
Clock.  If this function is not needed, this pin can be used as a general-purpose
output.
During Reset: Low After Reset: Low During POS: Low 
						

							Major Chips Description2-25Table 2-282371AB Pin DescriptionsNameTypeDescriptionGENERAL PURPOSE INPUT AND OUTPUT SIGNALSSome of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals. The usage
is determined by the system configuration.  The default pin usage is shown in Table 1 and Table 2. The
configuration can be selected via the General Configuration register and X-Bus Chip Select register.GPI[21:0]IGENERAL PURPOSE INPUTS. These input signals can be monitored via the
GPIREG register located in Function 3 (Power Management) System IO Space
at address PMBase+30h. See Table 1 for details.GPO[30:0]OGENERAL PURPOSE OUTPUTS. These output signals can be controlled via the
GPIREG register located in Function 3 (Power Management) System IO Space
at address PMBase+34h.
If a GPO pin is not multiplexed with another signal or defaults to GPO, then its
state after reset is the reset condition of the GPOREG register. If the GPO
defaults to another signal, then it defaults to that signal’s state after reset.  The
GPO pins that default to GPO remain stable after reset. The others may toggle
due to system boot or power control sequencing after reset prior to their being
programmed as GPOs.  The GPO8 signal is driven low upon removal of power
from the PIIX4 core power plane.  All other GPO signals are invalid (buffers
powered off).GPI SIGNALSSignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)NotesGPI0IOCHK#GPIGENCFG
Bit 0Available as GPI only if in EIO bus mode.GPI1#GPINon-multiplexed GPI which is always available. This
signal when used by power management logic is
active low.GPI[2:4]REQ[A:C]#GPIGENCFG
Bits 8–10Not available as GPI if used for PC/PCI. Can be
individually enabled, so for instance, GPI[4] is
available if REQ[C]# is not used.GPI5APICREQ#GPIXBCS
Bit 8Not available as GPI if using an external APIC.GPI6IRQ8#GPIGENCFG
Bit 14Not available as GPI if using external RTC or
external APIC.GPI7SERIRQGPIGENCFG
Bit 16Not available as GPI if using Serial IRQ protocol.GPI8THRM#THRM#GENCFG
Bit 23Not available as GPI if using thermal monitoring.GPI9BATLOW#BATLOW#GENCFG
Bit 24Not available as GPI if using battery low feature.GPI10LID#LIDGENCFG
Bit 25Not available as GPI if using LID feature.GPI11SMBALERT#SMBALERT#GENCFG
Bit 15Not available as GPI if using SMBALERT featureGPI12RI#RI#GENCFG
Bit 27Not available if using ring indicator featureGPI[13:21]GPINon-multiplexed GPIs which are always available. 
						

							2-26Service GuideSignalNameMultiplexedWithDefaultControl Registerand Bit (PCIFunction 1)NotesGPO0GPONon-multiplexed GPO which is always available.GPO[1:7]LA[17:23]GPOGENCFG
Bit 0Available as GPO only if EIO mode.GPO8GPONon-multiplexed GPO which is always available.
The GPO[8] signal will be driven low upon removal
of power from the PIIX4 core power plane.GPO[9:11]GNT[A:C]#GPOGENCFG
Bits [8:10]Not available as GPO if using for PC/PCI. Can be
individually enabled, so GPO[11] is available if
REQ[C]# not used.GPO12APICACK#GPOXBCS
Bit 8Not available as GPO if using external APIC.GPO13APICCS#GPOXBCS
Bit 8Not available as GPO if using external APIC.GPO14IRQ0GPOXBCS
Bit 8Not available as GPO if using external APIC.GPO15SUSB#SUSB#GENCFG
Bit 17Not available as GPO if using for power
management.GPO16SUSC#SUSC#GENCFG
Bit 17Not available as GPO if using for power
management.GPO17CPU_STP#CPU_STP#GENCFG
Bit 18Not available as GPO if using for clock control.GPO18PCI_STP#PCI_STP#GENCFG
Bit 19Not available as GPO if using for clock control.GPO19ZZZZGENCFG
Bit 20Not available as GPO if using for power
management.GPO20SUS_STAT1#SUS_STAT1#GENCFG
Bit 21Not available as GPO if using for power
management.GPO21SUS_STAT2#SUS_STAT2#GENCFG
Bit 22Not available as GPO if using for power
management.GPO22XDIR#XDIR#GENCFG
Bit 28Not available as GPO if using X-bus transceiver.GPO23XOE#XOE#GENCFG
Bit 28Not available as GPO if using X-bus transceiver.GPO24RTCCS#RTCCS#GENCFG
Bit 29Not available as GPO if using external RTC that
doesn’t do self decode.GPO25RTCALERTCALEGENCFG
Bit 30Not available as GPO if using external RTC that
doesn’t do self decode.GPO26KBCCS#KBCCS#GENCFG
Bit 31Not available as GPO if using external KBC that
doesn’t do self decode.GPO[27:28]GPONon-multiplexed GPOs which are always available.GPO29IRQ9OUT#GPOXBCS
Bit 8Not available as GPO if using external APIC. This
signal is used for IRQ9 output in APIC mode, where
it is level triggered, active low.GPO30GPONon-multiplexed GPO which is always available.Table 2-282371AB Pin Descriptions (continued)NameTypeDescriptionOTHER SYSTEM AND TEST SIGNALS 
						

							Major Chips Description2-27Table 2-282371AB Pin Descriptions (continued)NameTypeDescriptionCONFIG1ICONFIGURATION SELECT 1. This input signal is used to select the type of
microprocessor being used in the system. If CONFIG1=0, the system contains
a Pentium microprocessor. If CONFIG1=1, the system contains a Pentium II
microprocessor. It is used to control the polarity of INIT and CPURST signals.CONFIG2ICONFIGURATION SELECT 2. This input signal is used to select the positive or
subtractive decode of FFFF0000h–FFFFFFFFh memory address range (top
64 Kbytes).  If CONFIG[2]=0, the PIIX4 will positively decode this range. If
CONFIG[2]=1, the PIIX4 will decode this range with subtractive decode
timings only. The input value of this pin must be static and may not
dynamically change during system operations.PWROKIPOWER OK. When asserted, PWROK is an indication to PIIX4 that power and
PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, PIIX4 asserts CPURST,
PCIRST# and RSTDRV. When PWROK driven active (high), PIIX4 negates
CPURST, PCIRST#, and RSTDRV.SPKROSPEAKER. The SPKR signal is the output of counter timer 2 and is internally
“ANDed” with Port 061h bit 1 to provide the Speaker Data Enable. This signal
drives an external speaker driver device, which in turn drives the ISA system
speaker.
During Reset: Low After Reset: Low During POS: Last StateTEST#ITEST MODE SELECT. The test signal is used to select various test modes of
PIIX4.  This signal must be pulled up to VCC(SUS) for normal operation.POWER AND GROUND PINSVCCV
CORE VOLTAGE SUPPLY. These pins are the primary voltage supply for the
PIIX4 core and IO periphery and must be tied to 3.3V.VCC (RTC)V
RTC WELL VOLTAGE SUPPLY. This pin is the supply voltage for the RTC
logic and must be tied to 3.3V.VCC (SUS)V
SUSPEND WELL VOLTAGE SUPPLY. These pins are the primary voltage
supply for the PIIX4 suspend logic and IO signals and must be tied to 3.3V.VCC (USB)V
USB VOLTAGE SUPPLY. This pin is the supply voltage for the USB
input/output buffers and must be tied to 3.3V.VREFV
VOLTAGE REFERENCE. This pin is used to provide a 5V reference voltage
for 5V safe input buffers.  VREF must be tied to 5V in a system requiring 5V
tolerance. In a 5V tolerant system, this signal must power up before or
simultaneous to VCC. It must power down after or simultaneous to VCC.  In a
non-5V tolerant system (3.3V only), this signal can be tied directly to VCC.
There are then no sequencing requirements.VSSV
CORE GROUND. These pins are the primary ground for PIIX4.VSS (USB)V
USB GROUND. This pin is the ground for the USB input/output buffers. 
						

							2-28Service Guide2.3 NM2160
The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2
Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock
synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a
high speed glueless 32-bit PCI 2.1 compliance interface.
By integrating the display buffer DRAM and 128-bit graphics/video accelerator, the NM2160 achieves the
leading performance in the smallest footprint available. The NM2160 has sufficient bandwidth to perform
full-screen, 30fps video acceleration of MPEG, Indeo, Cinepak, and other video playback CODECs. The
bandwidth headroom also allows the NM2160 to deliver the highest quality video playback of any
notebook graphics solution, without compromising simultaneous graphics performance.
The unique integration of the NM2160 also allows the NM2160 to consume 70% less power than
equivalent video solutions, with fewer chips and less board space.
2.3.1 Features
· 128 Bit Graphics Acceleration
· High speed BitBLT Engine
· Color Expansion
· Accelerated Text Hardware
· Clipping
· X-Y Coordinates Addressing
· Memory Mapped I/O
· Bus Mastering
· Z-Buffer data stripping
· VGA I/O relocatable to MMIO Space
· Video Acceleration
· Integrated frame buffer for Video and Graphics
· 16M Color video in all modes
· Color space Conversion(YUV to RGB)
· Arbitrary video scaling up to 8X ratio
· Bilinear interpolation and Filtering
· Video Overlay capability from on/off screen memory
· Color Key Support
· Independent Brightness Control for Video Window
· Supports different color depths between video and graphics
· Supports RGB graphics and video in YUV format in one Integrated frame buffer
· Continuous down scaling independent of X&Y direction
· Memory Support 
						

							Major Chips Description2-29· High Speed 2Mbytes of integrated DRAM
· 128 bit Memory Interface
· Bus Support
· PCI 2.1 compliance Local Bus(Zero wait states)
· 3.3Volts or 5Volts operation
· EMI Reduction
· Spread Spectrum Clocking technology for reduced panel EMI
· Hardware Cursor and Icon
· Relocatable Hardware Cursor and Icon
· 64X64 Hardware Cursor
· 64X64 or 128X128 Hardware Icon
· Green PC Support
· VESA Display Power management(DPMS)
· DAC Power Down modes
· Suspend/Standby/Clock management
· VGA disable support
· PCI Mobile Computing “clockrun” support
· Resolution and Color Support
· VGA: TFT, DSTN, CRT@85Hz(640X480 256, 64k, 16M)
· SVGA: TFT, DSTN, CRT@85Hz(800X600 256, 64k, 16M)
· XGA: TFT, DSTN, CRT@75Hz(1024X768 256, 64k, Colors)
· Simultaneous CRT/Flat Panel operation
· Simultaneous TV/Flat Panel operation
· Display Enhancements
· TV Out Support
· ZV(Zoomed Video) Port
· 24 Bit Integrated RAMDAC with Gamma Correction
· 36 bit panel support
· Hardware expansion for low-resolution display mode compensation to panels
· Virtual Screen Panning Support
· Integrated Dual Clock Synthesizer
· VESA DDC1 and DDC2b 
						

							2-30Service Guide2.3.2 Pin DiagramFigure 2-3NM2160 Pin Diagram 
						

							Major Chips Description2-312.3.3 Pin Descriptions
Conventions used in the pin description types:
IInput into NM2160
OOutput from NM2160
I/OInput and Output to/from NM2160
T/STri-state during un-driven state
S/T/SBefore becoming tri-state the pin will be driven inactive
O/DOpen-drain type output
Table 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescriptionPCI Interface61
60
58
56
55
54
53
52
50
49
48
47
46
45
43
41
39
38
37
36
35
34
33
32
30
28
26
24
22
21
20
19AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0I/O
T/SMultiplexed Address and Data 31:0 These multiplexed and bi-
directional pins are used to transfer address and data on the PCI
bus. The bus master will drive the 32-bit physical address during
address phase and data during data phase for write cycles.
NM2160 will drive the data bus during data phase for read cycles63
51
40
31C/BE3#
C/BE2#
C/BE1#
C/BE0#I/O
Multiplexed Command and Byte Enable These multiplexed pins
provide the command during address phase and byte enable(s)
during data phase to the NM2160. NM2160 drives this pin in the
Bus Master mode 
						

							2-32Service GuideTable 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription72FRAME#I/O
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access. NM2160 drives
this pin in the Bus Master mode65PARI/O
Parity Even parity across AD31:0&C/BE3:0# is driven by the bus
master during address and write data phases and driven by
NM2160 during read data phases67TRDY#I/O
S/T/STarget ready This active low signal indicates NM2160’s ability to
complete the current data phase of the transaction. During a read
cycle TRDY# indicates that valid data is present on AD 31:00.
During a write, it indicates NM2160 is prepared to accept data.
Wait states will be inserted until both TRDY#&IRDY# are asserted
together. Input when NM2160 is in Bus Master68STOP#I/O
S/T/SStop This active low signal indicates that NM2160 is requesting
the master to terminate at the end of current transaction. Input
when NM2160 is in Bus Master69DEVSEL#I/O
S/T/SDevice Select This active low signal indicates that NM2160 has
decoded its address as the target of the current access. Input
when NM2160 is in Bus Master81IDSELI
Initialization Device Select This input signal is used as a chip
select during configuration read and write transactions71BCLKI
Bus Clock This input provides the timing for all transactions on
PCI bus66BREQ#O
T/SBus Request This active-low output is used to indicate the arbiter
that NM2160 desires use of the bus88BGNT#I
Bus Grant This active-low input indicates NM2160 that access to
the bus has been granted84RESET#I
Reset This active-low input is used to initialize NM216070INTA#O
O/DInterrupt request A This active low “level sensitive” output
indicates an interrupt request145CLKRUN#I/O
O/DClockrun The master device will control this signal to the
NM2160, according to the Mobile Computing PCI design guide.  If
this signal is sampled high by the NM2160 and the PCI clock
related functions are not completed then it will drive this signal
Low to request the Central Clock Resource for the continuation of
the PCI clock. This function can be Enabled/Disabled through
register GR12 bit 5Clock Interface93XTAL1/
14MHZI
Oscillator Input This pin is used to feed in a reference clock of
14.31818Mhz from an external oscillator OR a Clock Source to
the internal PLL. NM2160 CR70[5] can be programmed to provide
a 1Xfsc or 4xfsc NTSC sub-carrier frequency for an external
analog Encoder92XTAL2/
17MHZI
Oscillator Input This pin is used to feed in a reference clock of
17.734480Mhz from an external oscillator OR a Clock Source to
the internal PLL. NM2160 CR70[5] can be programmed to provide
a 1Xfsc or 4xfsc PAL/SECAM sub-carrier frequency for an
external Analog Encoder