Acer Travelmate 7100 Service Guide

							Major Chips Description2-63Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerPERR#
Parity Error: The CL-PD6832 drives this
output active (low) if it detects a data parity
error during a write phase.33I/O4SERR#
System Error: This output is pulsed by the CL-
PD6832 to indicate an address parity error.34O-
OD4PAR
Parity: This pin is sampled the clock cycle
after completion of each corresponding
address or write data phase. For read
operations this pin is driven from the cycle after
TRDY# is asserted until the cycle after
completion of each data phase. It ensures even
parity across AD[31:0] and C/BE[3:0]#.35I/O4PCI_CLK
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the
CL-PD6832. All PCI bus interface signals
described in this table, except RST#, INTA#,
INTB#, INTC#, and INTD#, are sampled on the
rising edge of PCI_CLK; and all CL-PD6832
PCI bus interface timing parameters are
defined with respect to this edge. This input
can be operated at frequencies from 0 to 33
MHz.1IRST#
Device Reset: This input is used to initialize all
registers and internal logic to their reset states
and place most CL-PD6832 pins in a high-
impedance state.207IINTA#/
IRQ9PCI Bus Interrupt A / ISA Interrupt Request
9: This output indicates a programmable
interrupt request generated from any of a
number of card actions. Although there is no
specific mapping requirement for connecting
interrupt lines from the CL-PD6832 to the
system, a common use is to connect this pin to
the PCI bus INTA# interrupt line and using PCI
Interrupt Signaling mode. In External-Hardware
Interrupt Signaling mode, this pin indicates
interrupt request IRQ9.203O-TS4Rl_OUT*/
INTB#/
IRQ10Ring Indicate Output / PCI Bus Interrupt B /
ISA Interrupt Request 10: In PCI Interrupt
Signaling mode, this output can be used as an
interrupt output connected to the PCI bus
INTB# interrupt line. If Misc Control 2 register
bit 7 is ‘1’, as a ring indicate output from a
socket’s BVD1/-STSCHG/-RI input. In External-
Hardware Interrupt Signaling mode, this pin
indicates interrupt request IRQ10.204O-TS4 
						

							2-64Service GuideTable 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerSOUT#/
INTC#/
ISLDSerial Interrupt Output / PCI Bus Interrupt C
/ Serial IRQ Load: In PCI Interrupt Signaling
mode, this output can be used as an interrupt
output connected to the PCI bus INTC#
interrupt line. In PC/PCI Serial Interrupt
Signaling mode, this pin is the serial interrupt
output, SOUT#. In External-Hardware Interrupt
Signaling mode, this pin is the load signal,
ISLD, used to load the serially transmitted
interrupt data into the external serial-to-parallel
shifters.205I/O4SIN#
/INTD#
/ISDATSerial Interrupt Input / PCI Bus Interrupt D /
Serial IRQ Data: In PCI Interrupt Signaling
mode, this output can be used as an interrupt
output connected to the PCI bus INTD#
interrupt line. In PC/PCI Serial Interrupt
Signaling mode, this pin is the serial interrupt
input, SIN#. In External-Hardware Interrupt
Signaling mode, this pin is the IRQ vector data,
ISDAT, that is serially transmitted to the
external serial-to-parallel shifters.206I/O4CLKRUN#
Clock Run: This pin is an input to indicate the
status of PCI_CLK and an open-drain output to
request the starting or speeding up of
PCI_CLK. This pin complies with the Mobile
PC/PCI Extended Interrupt Specification.208I/O4GNT#
Grant: This signal indicates that access to the
bus has been granted.2I4REQ#
Request: This signal indicates to the arbiter
that the CL-PD6832 requests use of the bus.3O4PCI_VCC
PCI Bus Vcc: These pins can be connected to
either a 3.3- or 5-volt power supply. The PCI
bus interface pin outputs listed in this table will
operate at the voltage applied to these pins,
independent of the voltage applied to other CL-
PD6832 pin groups.6, 21, 37, 50PWR 
						

							Major Chips Description2-65Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin No.(socket A)Pin No.(socketB)I/OPowerSocket Interface Pins-REG/
CC/BE3#Register Access: In Memory Card
Interface mode, this output chooses
between attribute and common memory. In
l/O Card Interface mode, this signal is
active (low) for non DMA transfers and high
for DMA  transfers.  In ATA mode this
signal is always high.  In CardBus mode,
this pin is the command and byte enables.112188I/O2 or 3A[25:24]/
CAD[19,17]PCMCIA socket address 25:24 outputs.
In CardBus mode, these pins are the
CardBus address/data bits 19 and 17,
respectively.102, 99176,
174I/O2 or 3A23/
CFRAME#PCMCIA socket address 23 output.  In
CardBus mode, this pin is the Cardbus
FRAME# signal.96172I/O2 or 3A22/
CTRDY#PCMCIA socket address 22 output.  In
CardBus mode, this pin is the Cardbus
TRDY# signal.94170I/O2 or 3A21/
CDEVSEL#PCMCIA socket address 21 output.  In
CardBus mode, this pin is the Cardbus
DEVSEL# signal.92168I/O2 or 3A20/
CSTOP#PCMCIA socket address 20 output.  In
CardBus mode, this pin is the Cardbus
STOP# signal.90166I/O2 or 3A19/
CBLOCK#PCMCIA socket address 19 output.  In
CardBus mode, this signal is the CardBus
LOCK# signal used for locked transactions.88164I/O2 or 3A18/
RFUPCMCIA socket address 18 output.  In
CardBus mode, this pin is reserved for
future use.85161O2 or 3A17/
CAD16PCMCIA socket address 17 output.  In
CardBus mode, this pin is the Cardbus
address/data bit 16.83158I/O2 or 3A16/
CCLKPCMCIA socket address 16 output.  In
CardBus mode, this pin supplies the clock
to the inserted card.93169O2 or 3A15/
CIRDY#PCMCIA socket address 15 output.  In
CardBus mode, this pin is the Cardbus
IRDY# signal.95171I/O2 or 3A14/
CPERR#PCMCIA socket address 14 output.  In
CardBus mode, this pin is the Cardbus
PERR# signal.86162I/O2 or 3 
						

							2-66Service GuideTable 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin No.(socket A)Pin No.(socketB)I/OPowerA13/
CPARPCMCIA socket address 13 output.  In
CardBus mode, this pin is the Cardbus PAR
signal.84159I/O2 or 3A12/
CC/BE2#PCMCIA socket address 12 output.  In
CardBus mode, this pin is the Cardbus
C/BE2# signal.97173I/O2 or 3A[11:9]/
CAD[12,9,14]PCMCIA socket address 11:9 outputs.  In
CardBus mode, these pins are the Cardbus
address/data bits 12, 9, and 14,
respectively.77, 73,
80153,
149,
155I/O2 or 3A8/
CC/BE1#PCMCIA socket address 8 output.  In
CardBus mode, this pin is the Cardbus
C/BE1# signal.82157I/O2 or 3A[7:0]/
CAD[18, 20-26]PCMCIA socket address 7:0 outputs.  In
CardBus mode, these pins are the Cardbus
address/data bits 18 and 20-26,
respectively.100,
103,
105,
107,
109,
111,
113,
116175,
178,
181,
183,
185,
187,
189,
191I/O2 or 3D15/
CAD8PCMCIA socket data I/O bit 15.  In
CardBus mode, this pin is the Cardbus
address/data bit 8.71148I/O2 or 3D14/
RFUPCMCIA socket data I/O bit 14.  In
CardBus mode, this pin is reserved for
future use.69145I/O2 or 3D[13:3]/
CAD[6,4,2,31, 30,
28, 7, 5, 3, 1, 0]PCMCIA socket data I/O bits 13:3.  In
CardBus mode, this pin is the Cardbus
address/data bit 6 4,2,31,30,28,7,5,3,1, and
0, respectively.67, 65,
63,
124,
122,
120,
68, 66,
64, 62,
59142,
140,
138,
199,
197,
195,
144,
141,
139,
137,
135I/O2 or 3D2/RFU
PCMCIA socket data I/O bit 2.  In
CardBus mode, this pin is reserved for
future use.123198I/O2 or 3D[1:0]/
CAD[29,27]PCMCIA socket data I/O bit 1:0.  In
CardBus mode, these pins are the Cardbus
address/data bits 29 and 27, respectively.121,
119196,
194I/O2 or 3 
						

							Major Chips Description2-67Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin No.(socket A)Pin No.(socketB)I/OPower-OE/
CAD11Output Enable: This output goes
active(low) to indicate a memory read from
the PCMCIA socket to the CL-PD6832.  In
CardBus mode, this pin is the Cardbus
address/data bit 11.75151I/O2 or 3-WE/
CGNT#Write Enable: This output goes active(low)
to indicate a memory write from the CL-
PD6832 to the PCMCIA socket.  In CardBus
mode, this pin is the CardBus GNT# signal.89165I/O2 or 3-IORD/
CAD13I/O Read: This output goes active (low) for
l/O reads from the socket to the CL-
PD6832.  In CardBus mode, this pin is the
CardBus address/data bit 13.78154I/O2 or 3-IOWR/
CAD15I/O Write: This output goes active (low) for
l/O writes from the CL-PD6832 to the
socket.  In CardBus mode, this pin is the
CardBus address/data bit 15.81156I/O2 or 3WP/
-IOIS16/
CCLKRUN#Write Protect / I/O Is 16-Bit: In Memory
Card Interface mode, this input is
interpreted as the status of the write protect
switch on the PCMCIA  card. In l/O Card
Interface mode, this input indicates the size
of the l/O data at the current address on the
PCMCIA card.  In CardBus mode, this pin is
the CardBus CLKRUN# signal, which starts
and stops the CardBus clock CCLK.125201I/O-
PU2 or 3-INPACK/
CREQ#Input Acknowledge: The -INPACK
function is not applicable in PCI bus
environments. However, for compatibility
with other Cirrus Logic products, this pin
should be connected to the PCMCIA
sockets -INPACK pin.  In CardBus mode,
this pin is the CardBus REQ# signal.110186I-PU2 or 3RDY/
-IREQ/
CINT#Ready / Interrupt Request: In Memory
Card Interface mode, this input indicates to
the CL-PD6832 that the card is either ready
or busy. In l/O Card Interface mode, this
input indicates a card interrupt request.  In
CardBus mode, this pin is the CardBus
Interrupt Request signal. This signal is
active-low and level-sensitive.91167I-PU2 or 3-WAIT/
CSERR#Wait: This input indicates a request by the
card to the CL-PD6832 to halt the cycle in
progress until this signal is deactivated.  In
CardBus mode, this pin is the CardBus
SERR# signal.108184 I-PU2 or 3 
						

							2-68Service GuideTable 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin No.(socket A)Pin No.(socketB)I/OPower-CD[2:1]/
CCD[2:1]#Card Detect: These inputs indicate to the
CL-PD6832  that a card is in the socket.
They are internally pulled high to the
voltage of the +5V power pin.  In CardBus
mode, these inputs are used in conjunction
with CVS[2:1] to detect the presence and
type of card.126, 61202,
136 I-PU1-CE2/
CAD10Card Enable pin is driven low by the CL-
PD6832 during card access cycles to
control byte/word card access. -CE1
enables even-numbered address bytes, and
-CE2 enables odd-numbered address bytes.
When configured for 8-bit cards, only -CE1
is active and A0 is used to indicate access
of odd- or even-numbered bytes.  In
CardBus mode, this pin is the CardBus
address/data bit 1074150I/O2 or 3-CE1/
CC/BE0#Card Enable pin is driven low by  the CL-
PD6832 during card access cycles to
control byte/word card access. -CE1
enables even-numbered address bytes, and
-CE2 enables odd-numbered address bytes.
When configured for 8-bit cards, only -CE1
is active and A0 is used to indicate access
of odd- or even-numbered bytes.  In
CardBus mode, this pin is the CardBus
C/BE0# signal.70147I/O2 or 3RESET/
CRST#Card Reset: This output is low for normal
operation and goes high to reset the card.
To prevent reset glitches to a card, this
signal is high-impedance unless a card is
seated in the socket, card power is applied,
and the cards interface signals are enabled.
In CardBus mode, this pin is the RST# input
to the card, which is active-low.106182O-
TS2 or 3BVD2/-SPKR/
-LED/CAUDIOBattery Voltage Detect 2 / Speaker / LED:
In Memory Card Interface mode, this input
serves as the BVD2 (battery warning status)
input. In l/O Card Interface mode, this input
can be configured as a cards -SPKR binary
audio input. For ATA or non-ATA (SFF-68)
disk-drive support, this input can also be
configured as a drive-status LED input.  In
CardBus mode, this pin is the AUDIO input
from the card.114190I-PU2 or 3 
						

							Major Chips Description2-69Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin No.(socket A)Pin No.(socketB)I/OPowerBVD1/
-STSCHG/
-RI/
-CSTSCHGBattery Voltage Detect 1 / Status Change
/ Ring Indicate: In Memory Card Interface
mode, this input serves as the BVD1
(battery-dead status) input. In I/O Card
Interface mode, this input is the -STSCHG
input, which indicates to the CL-PD6832
that the cards internal status has changed.
If bit 7 of the Interrupt and General Control
register is set to ‘1’, this pin serves as the
ring indicate input for wakeup-on-ring
system power management support.  In
CardBus mode, this pin is the CardBus
Status change used by the card to alert the
system to changes in READY, WP, and
BVD[2:1].118192I-PU2 or 3VS2/
CVS2Voltage Sense 2: This pin is used in
conjunction with VS1 to determine the
operating voltage of the card. This pin is
internally pulled high to the voltage of the
+5V power pin under the combined control
of the external data write bits and the CD
pull up control bits. This pin connects to
PCMCIA  socket pin 57.104179I/O1VS1/
CVS1Voltage Sense 1: This pin is used in
conjunction with VS2 to determine the
operating voltage of the card. This pin is
internally pulled high to the voltage of the
+5V power pin under the combined control
of the external data write bits and the CD
pull up control bits. This pin connects to
PCMCIA socket pin 43.76152I/O1SOCKET
_VCCConnect these pins to the Vcc supply of the
socket (pins 17 and 51 of the respective
PCMCIA socket). These pins can be 0, 3.3,
or 5 V, depending on card presence, card
type, and system configuration. The socket
interface out puts (listed in this table, Table
2-2) will operate at the voltage applied to
these pins, independent of the voltage
applied to other CL-PD6832 pin groups.117,
98, 79,
60200,180
, 160,
143PW
R 
						

							2-70Service GuideTable 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerPower Control and General Interface PinsSPKR_OUTt
Speaker Output: This output can be used as a
digital output to a speaker to allow a system to
support PCMCIA  card fax/modem/voice and
audio sound output.  This output is enabled by
setting the socket’s Misc Control 1 register bit 4
to ‘1’(for the socket whose speaker signal is to
be directed from BVD2/-SPKR/-LED to this
pin). This pin is used for configuration
information during hardware reset. Refer to
Misc Control 3 register bit 0.128I/O-
PU4LED_OUT/
HW_SUSPEND
#tLED Output: This output can be used as an
LED driver to indicate disk activity when a
sockets BVD2/-SPKR/-LED pin has been
programmed for LED support. The Extension
Control 1 register bit 2 must be set to ‘1’ to
enable this output(to reflect any activity on
BVD2/-SPKR/-LED), and a socket’s ATA
Control register bit 1 must be set to ‘1’ to allow
the level of  the BVD2/-SPKR/-LED pin to
reflect disk activity.
Serves as a HW_SUSPEND# input pin, when
Misc Control 3 register bit 4 is set to ‘1’.
This pin is used for configuration information
during hardware reset. Refer to Misc Control 3
register bit 1.133I/O-
PU4SCLK
Serial Clock: This input is used as a reference
clock (10-100 kHz, usually 32 kHz) to control
the serial interface of the socket power control
chips.  CAUTION: This pin must be driven at
all times.132ISDATA/
SMBDATAtSerial Data / System Management Bus Data:
This pin serves as output pin SDATA when
used with the serial interface of Texas
Instruments TPS2202AIDF socket power
control chip, and serves as a bidirectional pin
SMBDATA when used with Intels System
Management Bus used by Maxims socket
power control chip. This pin is open drain for
the SMB mode of operation and requires an
external pull up.
This pin is used for configuration information
during hardware reset. Refer to Misc Control 3
register bit 3.131I/O-
PU2 or 3 
						

							Major Chips Description2-71Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerSLATCH/
SMBLCKtSerial Latch / System Management Bus
Clock: This pin serves as output pin SLATCH
when used with the serial interface of Texas
Instruments TPS2202AIDF socket power
control chip, and serves as a bidirectional pin
SMBCLK when used with Intels System
Management Bus used by Maxims socket
power control chip. This pin is open drain in the
SMB mode of operation. In this mode an
external pull up is required.
This pin is used for configuration information
during hardware reset. Refer to misc Control 3
register bit 2.130I/O-
PU2 or3Power and Ground Pins+5VThis pin is connected to the systems 5-volt
power supply. In systems where 5 volts is not
available, this pin can be connected to the
systems 3.3-volt supply (but no 5volt
connections to the CL-PD8632 will be allowed).127PWRCORE_VDDThis pin provides power to the core circuitry of
the CL-PD6832. This pin must be connected to
the 3.3-volt supply.134PWRCORE_GNDAll CL-PD6832 ground lines should be
connected to system ground.26GNDRING_GNDAll CL-PD6832 ground lines should be
connected to system ground.14, 28, 44, 57, 72, 87, 101,
115, 129, 146, 163, 177,
193GND 
						

							2-72Service Guide2.8 Ambit T62.036.C DC-DC Converter
This T62.036.C DC-DC converter supplies multiple DC(5V, 3,3V, 12V) output to system, and also
supplies the battery charge current (0~3.5A).   The total inputs from the notebook would be limited
by the total output of 65 watts maximum.
2.8.1 Pin Diagram2 - VDCF
4 - VDCF
6 - GND
8 - DCIN
10 - DCIN
12 - CHARGON
14 - CHARGSP
16 - GND
18 - CHARGOUT
20 - CHARGOUTCN1VDCF - 1
VDCF - 3
GND - 5
DCIN - 7
DCIN - 9
CHARGCL - 11
CHARGFB - 13
GND - 15
CHARGOUT - 17
CHARGOUT - 192 - P12VR
4 - GND
6 - P3VR
8 - P3VR
10 - GND
12 - P3VRON
14 - P12VRON
16 - GND
18 - P5VRON
20 - P5VRONCN2P12VR - 1
GND - 3
P3VR - 5
P3VR - 7
GND - 9
BMCVCC - 11
BMCVCC - 13
GND - 15
P5VRON - 17
P5VRON - 19T62.036.C
Figure 2-11T62.036.C Pin Diagram
2.8.2 Pin Descriptions
Table 2-8T62.036.C Pin DescriptionsPin NamePin TypePin No.DescriptionCN1 signalsVDCFI1, 2, 3, 418VDC input from battery.DCINI7, 8, 9,
107~19VDC input from AC adapter.CHARGCLI11Enables Charger output.  This input is driven by an open drain
signal to set the charging current limit to a high (3 .5A max.) or
low (2A). The lower limit is set when the signal is low (switch on).
The system will generally set this signal low when the battery has
been discharged to a low level. The battery current sensor is built
into the charger circuitry. The resistance of the drain switch is
less than 1KW.
Note, this signal sets the limit value of the charging current. The
CHARGFB and CHARGSP signals may restrict the charging
current to a lower level.CHARGONI12This is a logic level signal, active high to enable the adapter
current output. This signal allows the system board to turn off the
charger output whenever the battery pack reports unsafe
conditions such as over temperature, error or no communication.
It may be used in response to any other detectable unsafe
system conditions ±1uA maximum loading.CHARGFBI13This signal is provided by a current sensor in the system to