Acer Travelmate 7100 Service Guide
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1-18Service Guide1.5.2 Media BoardCN2 CN1CN4CN5CN6 CN2Lid switch CN1LCD connectorCN6Touchpad connector CN4, CN5Keyboard connector Figure 1-11Media Board Jumpers and Connectors (Top Side)CN9CN7 CN8 CN7, CN8Mainboard connectorCN9PCMCIA socket connector Figure 1-12Media Board Jumpers and Connectors (Bottom Side)
System Introduction1-191.6 System Configurations and Specifications 1.6.1 System Memory Map Table 1-8System Memory MapAddress RangeDefinitionFunction000000 -09FFFF640 KB memoryBase memory0A0000 -0BFFFF128 KB video RAMReserved for graphics display buffer0C0000 -0CBFFFVideo BIOSVideo BIOS0CC000 -0CDFFF 0CE000 -0CFFFFSystem CardBus Mini dock CardBus0F0000 -0FFFFF64 KB system BIOSSystem BIOS010000 -07FFFF 080000 -027FFFExtended memoryOnboard memory SIMM memoryFE0000 -FFFFFF256 KB system ROMDuplicate of code assignment at 0E0000-0FFFFF1.6.2 Interrupt Channel Map Table 1-9Interrupt Channel MapInterrupt NumberInterrupt Source (Device Name)IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 8 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 13 IRQ 14 IRQ 15System Timer Keyboard Cascade IrDA / 2F8h Serial Port 1 / 3F8h Audio Floppy Disk Controller (FDC) Parallel Port Real Time Clock (RTC) USB/System CardBus Reserved for PCMCIA card Reserved for PCMCIA card/Mini dock CardBus PS/2 Mouse Co-processor Hard disk CD-ROM1.6.3 I/O Address Map Table 1-10I/O Address MapAddress RangeDevice000 -00F 020 -021 02E -02F 040 -043 048 -04BDMA controller-1 Interrupt controller-1 NS87338 peripheral controller Timer 1 Timer 2
1-20Service GuideTable 1-10I/O Address MapAddress RangeDevice060 -06E 070 -071 080 -08F 0A0 -0A1 0C0 -0DF 1F0 -1F7 3F6 -3F7 170 -177 376 -377 220 -22F 240 -24F 260 -26F 280 -28F 278 -27F 2E8 -2EF 2F8 -2FF 300 -301 310 -311 320 -321 330 -321 378 -37F 388 -38B 3BC -3BE 3B4, 3B5, 3BA 3C0 -3C5 3C6 -3C9 3C0 -3CF 3D0 -3DF 3E8 -3EF 3F0 -3F7 3F8 -3FF CF8 -CFFKeyboard controller chip select Real-time clock and NMI mask DMA page register Interrupt controller-2 DMA controller-2 Hard disk select Hard disk select CD-ROM select CD-ROM select Audio Audio -default Audio Audio Parallel port 3 COM 4 COM 2 -IrDA MPU-401 port -default MPU-401 port MPU-401 port MPU-401 port Parallel port 2 FM synthesizer Parallel port 1 Video subsystem Video DAC Enhanced graphics display Color graphics adapter COM3 Floppy disk controller COM 1 -Serial 1 PCI configuration register1.6.4 DMA Channel Map Table 1-11DMA Channel MapControllerChannelAddressFunction1 1 1 1 2 2 2 20 1 2 3 4 5 6 70087 0083 0081 0082 Cascade 008B 0089 008AAudio(default) / IrDA(option) Audio(default) / ECP(option) / IrDA(option) Diskette Audio (option) / FIR IrDA(option) / ECP(option) Cascade Spare
System Introduction1-211.6.5 GPIO Port Definition Map Table 1-12GPIO Port Definition Map IGPIO/SignalPin #I/ODescriptionGPIO Pin Assignment: PIIX4SUSA# (PX3_SUSA#)W20O0: Power down clock generatorGPO0 (PX3_DOCKRST#)G4O0 : Enable docking resetGPO1 (PX3_HDPON)Y15O1: Turn on HDD powerGPO2 (PX3_ CD/FDPON)T14O1: Turn on CD/FDD powerGPO3 (PX3_ HDRST#)W14O0: Reset HDD interfaceGPO4 (PX3_CDRST#)U13O0: Reset CD interfaceGPO5 (PX3_3MODE)V13O0: 3 mode driveGPO6 (PX3_SMBSEL0)Y13OSelect one of three SM busesGPO7 (PX3_SMBSEL1)T12OSMBSEL1SMBSEL0 00DRAM bank 0 SMB 01DRAM bank 1 SMB 10MMO LM75 & clock gen. SMB 11PCMCIA LM75GPO8 (PX3_DOCKGNT#)T19O0: Granted dockingGPO9/GNTA# (PX3_VDPD)N1O1: Power down VGAGPO10/GNTB# (PX3_VGADIS)P2O1: Disable VGA from PCIGPO11/GNTC# (PX3_AUDPON)P4O1: Power on analog audio powerGPO12/APICACK#J17ONCGPO13/APICCS#H18ONCGPO14/IRQ0 (PX3_ROM#)H20O0: Enable ROMCS#GPO15/SUSB#V19ONCGPO16/SUSC#U18ONCGPO17/CPU_STP#(PX3_CPUSTP#)R1O0: Enable CPU clock stopGPO18/PCI_STP# (PX3_PCISTP#)R2O0: Enable PCI clock stopGPO19/ZZ (PXI_L2ZZ)K16O1: Power down L2 cacheGPO20/SUS_STAT1#(PX3_SUSTAT#)T17O0: Enable MTXC power downGPO21/SUS_STAT2# (PM3_A_ACT/PD#)T18O0: Power down PD6832 Cardbus controllerGPO22/XDIR# (PX3_FDDBEN)M3O1: FDD buffer enableGPO23/XOE# (PX3_SPPD)M4O1: Power down serial interfaceGPO27 (PX3_SPKOFF)G5O1: Turn off speakerGPO28 (PX3_FLASHVPP)F2O1: Enable Flash Vpp controlGPO29 (PX3_FPAGE1)F3OForce BIOS to high page 1F segment and 3 E segmentsGPO30 (PX3_FPAGE2)F4OFPAGE2FPAGE1 00F, E0 01F, E1 10F, E2 11reservedEXTSMI#(PX3_KRSMIREQ#)V20O0: Enable by KBD SMI or RTC wake
1-22Service GuideTable 1-12GPIO Port Definition Map IGPIO/SignalPin #I/ODescriptionGPI1 (DK3_DOCKIRQ#)P19O0: Detect Docking IRQGPI2/REQA# (PX3_OEM0)M1OOEM detectionGPI3/REQB# (SM5_BAYSW)N2ODetect FDD/CD bay 1: installed, 0: not installedGPI4/REQC# (CF5_FDD/CD#)P3ODetect FDD or CD installed 1: FDD, 0: CDGPI5/APICREQ#K18ONCGPI6/IRQ8# (RT3_IRQ8#)Y20O0: RTC wakeGPI7/SERIRQ (PM3_IRQSER)J19OSerial IRQGPI8/THRM# (SM5_OVTMP#)H19O0: Enable over temperature of CPU or systemGPI9/BATLOW# (PX3_OEM1)U19IOEM detectionGPI10/LIDP16INCGPI11/SMBALER#N17INCGPI12/RI# (PX3_RI#)P18I0: Enable by Ring indicator inputGPI13 (PT3_MID0)L2IDetect MMO module revisionGPI14 (PT3_MID1)J3IDetect MMO module revisionGPI15 (PT3_MID2)L5IDetect MMO module revisionGPI16 (PT3_MID3)K3IDetect MMO module revisionGPI17 (SM5_FLOATREQ#)K4IDetect float request from SMCGPI18 (PX3_FLASHRCY#)H1I0: Enable flash BIOS recoveryGPI19 (PX3_VGACT)H4I1: Detect VGA activityGPI20 (PM3_A_ACT/PD#)H5IDetect PCMCIA socket A activity for OZ6832GPI21 (PM3_B_ACT)G3IDetect PCMCIA socket B activityTable 1-13GPIO Port Definition Map IIGPIOI/ODescriptionGPIO Pin Assignment: 80C51SLLED 0 (KB5_MIREQ#)OANI3 (KB5_PANID3)LED 1 (KB5_NUMLED#)OPAD LED controlLED 2 (KB5_CAPLED#)OCAP LED controlLED 3 (KB5_KEYLICK)OKeyclick outputP1.0ONCP1.1ONCP1.2ONCP1.3ONCP1.4ONCP1.5ONCP1.6ONC
System Introduction1-23Table 1-13GPIO Port Definition Map IIGPIOI/ODescriptionP1.7 (IS5_IRQ12)OIRQ12P2.0 (KB5_MEMB0A0)IAddress 0 of memory bank 0P2.1 (KB5_MEMB0A1)IAddress 1 of memory bank 0P2.2 (KB5_MODE)IDetect KBD mode (1:US/EC 0:Japan)P2.3INCP2.4 (KB5_MEMB1A0)IAddress 0 of memory bank 1P2.5 (KB5_PSWD)IEnable PasswordP2.6 (KB5_MEMB1A1)IAddress 1 of memory bank 1P2.7 (PX3_OEM0)IAddress 1 of memory bank 1P3.0 (SM5_TXD)IReceiving data from SMC to KBCP3.1 (SM5_RXD)OTransmitting data from KBC to SMCP3.2 (KB5_KBDCLK)OExternal KB clockP3.3 (KB5_PTRCLK)OExternal PS/2 clockP3.4 (KB5_KBDDAT)OExternal KB dataP3.5 (KB5_PTRDAT)OExternal PS/2 dataP3.6 (KB5_TOUCHWR*)OWrite enable touch pad dataP3.7 (KB5_TOUCHRD*)ORead enable touch pad dataANI0 (KB5_PANID0)IPanel IDANI1 (KB5_PANID1)IPanel IDANI2 (KB5_PANID2)IPanel IDANI3 (KB5_PANID3)IPanel ID: 3 2 1 0 0 0 0 0 12.1” TFTGPIO Pin Assignment: 83C552P0.0(SM5_CHARGEON#)OCharge control enableP0.1ONCP0.2 (SM5_BMCPWREN#)OBMC VCC power enableP0.3 (SM5_P3/5VRON#)O3V and 5V power onP0.4 (SM5_SUSPEND)OSuspend control enableP0.5 (SM5_PWRLED#)OPower LEDP0.5 (SM5_PWRLED#)OBattery LEDP0.7 (SM5_SMIREQ#)OSMC SMI requestP1.0 (SI5_PNF)IDetect Printer or external FDD 0: FDD 1: PrinterP1.1 (SM5_1WIRE)IODallas protocolP1.2 (SM5_UNDOCK_REQ#)IUndocked requestP1.3 (PX3_CPUSTP#)IDetect CPU clock stopP1.4 (SM5_ATN#)IOI2C inturruptP1.5 (SM5_RST#)IOI2C resetP1.6 (SM5_CLK#)IOI2C clockP1.7 (SM5_DAT#)IOI2C data
1-24Service GuideTable 1-13GPIO Port Definition Map IIGPIOI/ODescriptionP2.0INCP2.1ONCP2.2 (SM5_BAYSW)IDetect FDD/CD bay installed or notP2.3ONCP2.4ONCP2.5ONCP2.6ONCP2.7ONCP3.0 (SM5_RXD)IReceiving data from KBC to SMCP3.1 (SM5_TXD)OTransmitting data from SMC to KBCP3.2 (SM5_DOCKSW)IDock switch senseP3.3 (CF5_DOCKED)IDetect completely docked or notP3.4 (SM5_LIDSW)ILid switch senseP3.5 (SM5_OVTMP#)OCPU or system over temperatureP3.6ONCP3.7 (SM5_ON_RES_SW)OON/RESUME switch for Japan versionP4.0 (SM5_FANON)OFan controlP4.1NCP4.2 (SM5_FLOATREQ#)ODocking float requestP4.3 (SM5_UNDOCK_GNT#)OUndock grantP4.4 (SM5_ICONT)ICharge current controlP4.5 (SM5_FLAOTGNT#)IDocking float grantP4.6 (SM5_PWRRDYB)OPower ready, delay about 4ms after power goodP4.7 (SM5_SYSRDY)ONCP5.0 (CHARGSP)ICharging set pointP5.1 (SM5_VBAT_MAIN)IMain battery detectionP5.2 (SM5_ACPWRGD)IAC source power goodP5.3 (SM5_NBPWRGD)I3V, 5V, processor module power goodP5.4 (SM5_ATFINT)ICPU thermal interrupt (panic)P5.5 (SM5_THERM_SYS)ISystem thermal input (analog)P5.6 (SM5_ACIN_AUX)IAux AC adapter inP5.7 (SM5_ACIN_MAIN)IMain AC adapter inPWM1# (SM5_CONT)OLCD contrastPWM0# (SM5_BRIT)OLCD brightness1.6.6 PCI Devices Assignment Table 1-14PCI Devices Assignment
System Introduction1-25DeviceDevice IDAssignmentMTXC North Bridge0AD11PIIX4 ISA Bridge1AD18 (Function 0)PIIX4 IDE controller1AD18 (Function 1)PIIX4 USB controller1AD18 (Function 2)PIIX4 PM/SMBUS controller1AD18 (Function 3)PCI VGA(NM2160)2AD13PCI Cardbus controllerAAD21PCI Ethernet (Am79C970A) (ACER Dock III)CAD23PCI CardBus (TI 1131) (ACER Dock V)CAD231.6.7 Power Management Power Management in this design is aimed toward the conservation of power on the device and system level when the devices or system is not in use. This implies that if any device is detected as not active for a sustained period of time, the device will be brought to some lower power state as soon as practicable. With the exception of thermal management, if a device has a demand upon it, full performance and bandwidth will be given to that device for as long as the user demands it. Power management should not cause the user to sacrifice performance or functionality in order to get longer battery life. The longer battery life should be obtained through managing resources not in use. Pathological cases of measuring CPU speed or trying to periodically check for reaction time of specific peripherals can detect the presence of power management. However, in general, since the device I/O is trapped and the device managed in SMI, the power management of devices should be invisible to the user and the application. Thermal management is the only overriding concern to the power management architecture. By definition, thermal management only comes into play when the resources of the computer are used in such a way as to accumulate heat and operate many devices at maximum bandwidth to create a thermal problem inside the unit. This thermal problem indicates a danger of damaging components due to excessively high operating temperatures. Hence, in order to maintain a safe operating environment, there may be occasions where we have to sacrifice performance in order to achieve operational safety. Heuristic power management is designed to operate and adapt to the user while the user is using it. It is the plug and play equivalent for power management. There are no entries in BIOS Setup which are required to be set by the user in order to optimize the computers battery life or operation. The only BIOS Setup entries are for condition information for suspend/resume operations. Normal operations and power management are done automatically. (see chapter 3 for details).Since the power management is implemented by linking with APM interface closely, the APM function in Win95 or Win3.1 must be enabled and set to advanced level for optimum power management and the driver that installed in system must be Acer authorized and approved.
1-26Service Guide1.6.7.1 PMU Timers There are several devices related timers available on the V1-LS chip. Each timer may have zero or more devices assigned to the timer for the purpose of retriggering the timer. Table 1-15PMU Timers ListItemDescriptionsVideo timerTimer value30sec, 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min, 4.5min, 5min, 6min, 7min, 8min, 9min, 10min, 15min, 20min, 30min(if AC plugged-in)System activities and timer retriggersSystem activities - The video display (CRT and LCD) is in power saving mode. Timer retriggers - KBC, PS/2 mouse will retrigger the timer..Detective hardware changeParallel/serial timerTimer valueParallel port/COM1/COM2/FIR: 30secSystem activities and timer retriggersSystem activities - Parallel/serial port pins are in standby mode, serial port clock is stopped and parallel port and UART1 decode in the 87338 chip is disabled. Timer retriggers - Parallel port/COM1/COM2/FIR activitiesDetective hardware changeCOM1: The pin-25 of U4 MAX3243 (PX3-SPPD#) is from H to L.Hard disk timerTimer valueFirst phase heuristic time-out table for entering HDD standby mode: 10sec, 20sec, 30sec, 40sec, 50sec, 60sec, 70sec, 80sec, 90sec, 2min, 3min, 4min, 5min, 30min(if AC plugged-in) Second phase fixed timer for entering HDD suspend mode: 10secSystem activities and timer retriggersSystem activities - First phase time-out (heuristic) results in hard disk spin down and IDE interface disable. The second time-out (10sec) results in hard disk power off and IDE controller clock is stopped and its internal HDD buffer disabled. Timer retriggers - The I/O access to 1F0-7, 3F6 will retrigger the timer.Detective hardware change1. The U20 pin Y15(PX3_HDPON) is from H to L, HDD is powered off.FDD/CD-ROM timerTimer valueThe system with internal floppy: 30sec The system with internal CD-ROM1 : 1min, 2min, 3min, 4min, 5min, 6min, 7min, 8min, 9min, 10min, 15min, 30min(AC) 1 This parameter is for both internal CD-ROM and external floppy.
System Introduction1-27Table 1-15PMU Timers ListItemDescriptionsSystem activities and timer retriggersSystem activities - Power off either or both FDD and CD-ROM. Tri-state FDD and CD-ROM interfaces and stop IDE controller clock. Timer retriggers - The I/O access to 3F2, 3F4, 3F5(FDD), 3F7, 376(CD ROM) will retrigger the timer.Detective hardware change1. The PX3_FDDBEN signal on pin-M3 of U21(PIIX4) is from L to H. CD-ROM buffer is disabled. 2. The pin-T14(PX3_CD/FDPON) of U21(PIIX4) is from H to L, the FDD/CD-ROM is powered off.1.6.7.2 Component activities in power saving mode · Hard disk The hard disk is fully power managed. This means that when the hard disk is not in use, the hard disk is powered off. The following pins are dedicated toward the management of power on the hard disk. 1. HDD power enable pinY15(PX3_HDPON). This pin turns the power on/off for the hard disk only. 2. HDD reset [pinW14(PX3_HDRST#) of PIIX4]. This pin provides the reset to the drive when the drive is newly powered up. The reset pin is asserted when the drive is first powered up, then the reset is removed after the drive is powered up and before the interface is enabled. · CD-ROM The CD-ROM and the hard disk are both IDE devices. They share the same controller. The following pins are dedicated toward the management of power on the CD-ROM. 1. CD-ROM buffer enable [pin-M3 of U21 PX3-FDDBEN of PIIX4]. The CD buffer enable separates the CD-ROM from the IDE controller. This buffer must be disabled before the CD-ROM is turned off. The buffer is re-enabled after the CD-ROM is turned on and brought out of reset. 2. CD-ROM power control [pin-T14 of U21(PX3_CD/FDPON) of PIIX4]. The power control pin is used to turn the CD-ROM unit off or on. This pin is shared as a power on/off pin for the floppy disk as well.If either the internal or external floppy or the CD-ROM is active, then this control pin must be asserted on.