Acer Travelmate 7100 Service Guide

							Major Chips Description2-13Table 2-282371AB Pin DescriptionsNameTypeDescriptionSA[19:0]I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the
selection with the granularity of 1 byte within the 1-Megabyte section of memory
defined by the LA[23:17] address lines. The address lines SA[19:17] that are
coincident with LA[19:17] are defined to have the same values as LA[19:17] for
all memory cycles.  For I/O accesses, only SA[15:0] are used, and SA[19:16] are
undefined. SA[19:0] are outputs when PIIX4 owns the ISA Bus. SA[19:0] are
inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SASBHE#I/O
SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is
being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is
negated during refresh cycles. SBHE# is an output when PIIX4 owns the ISA
Bus. SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: HighSD[15:0]I/O
SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on
the ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond
to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-ZSMEMR#O
STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA
memory slave to drive data onto the data lines. If the access is below the 1-
Mbyte range (00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or
ISA master cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of
MEMR#.
During Reset: High-Z After Reset: High During POS: HighSMEMW#O
STANDARD MEMORY WRITE. PIIX4 asserts SMEMW# to request an ISA
memory slave to accept data from the data lines. If the access is below the 1-
Mbyte range (00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or
ISA master cycles, PIIX4 asserts SMEMW#. SMEMW# is a delayed version of
MEMW#.
During Reset: High-Z After Reset: High During POS: HighZEROWS#I
ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no
effect during 16-bit I/O cycles.  If IOCHRDY is negated and ZEROWS# is
asserted during the same clock, then ZEROWS# is ignored and wait states are
added as a function of IOCHRDY.X-BUS INTERFACEA20GATEI
ADDRESS 20 GATE. This input from the keyboard controller is logically
combined with bit 1 (FAST_A20) of the Port 92 Register, which is then output via
the A20M# signal.BIOSCS#O
BIOS CHIP SELECT. This chip select is driven active during read or write
accesses to enabled BIOS memory ranges. BIOSCS# is driven combinatorially
from the ISA addresses SA[16:0] and LA[23:17], except during DMA cycles.
During DMA cycles, BIOSCS# is not generated.
During Reset: High After Reset: High During POS: High 
						

							2-14Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionKBCCS#/
GPO26O
KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O
read or write accesses to KBC locations 60h and 64h. It is driven combinatorially
from the ISA addresses SA[19:0] and LA[23:17].  If the keyboard controller does
not require a separate chip select, this signal can be programmed to a general
purpose output.
During Reset: High After Reset: High During POS: High/GPOMCCS#O
MICROCONTROLLER CHIP SELECT. MCCS# is asserted during I/O read or
write accesses to IO locations 62h and 66h. It is driven combinatorially from the
ISA addresses SA[19:0] and LA[23:17].
During Reset: High After Reset: High During POS: HighPCS0#
PCS1#O
PROGRAMMABLE CHIP SELECTS. These active low chip selects are asserted
for ISA I/O cycles which are generated by PCI masters and which hit the
programmable I/O ranges defined in the Power Management section. The X-Bus
buffer signals (XOE# and XDIR#) are enabled while the chip select is active.
(i.e., it is assumed that the peripheral which is selected via this pin resides on
the X-Bus.)
During Reset: High After Reset: High During POS: HighRCIN#I
RESET CPU. This signal from the keyboard controller is used to generate an
INIT signal to the CPU.RTCALE/
GPO25O
REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the
appropriate memory address into the RTC. A write to port 70h with the
appropriate RTC memory address that will be written to or read from causes
RTCALE to be asserted.  RTCALE is asserted on falling IOW# and remains
asserted for two SYSCLKs.  If the internal Real Time Clock is used, this signal
can be programmed as a general purpose output.
During Reset: Low After Reset: Low During POS: Low/GPORTCCS#/
GPO24O
REAL TIME CLOCK CHIP SELECT. RTCCS# is asserted during read or write
I/O accesses to RTC location 71h. RTCCS# can be tied to a pair of external OR
gates to generate the real time clock read and write command signals. If the
internal Real Time Clock is used, this signal can be programmed as a general
purpose output.
During Reset: High After Reset: High During POS: High/GPOXDIR#/
GPO22O
X-BUS TRANSCEIVER DIRECTION. XDIR# is tied directly to the direction
control of a 74’245 that buffers the X-Bus data, XD[7:0]. XDIR# is asserted
(driven low) for all I/O read cycles regardless if the accesses is to a PIIX4
supported device. XDIR# is asserted for memory cycles only if BIOS or APIC
space has been decoded. For PCI master initiated read cycles, XDIR# is
asserted from the falling edge of either IOR# or MEMR# (from MEMR# only if
BIOS or APIC space has been decoded), depending on the cycle type. For ISA
master-initiated read cycles, XDIR# is asserted from the falling edge of either
IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),
depending on the cycle type. When the rising edge of IOR# or MEMR# occurs,
PIIX4 negates XDIR#. For DMA read cycles from the X-Bus, XDIR# is driven low
from DACKx# falling and negated from DACKx# rising. At all other times, XDIR#
is negated high.  If the X-Bus not used, then this signal can be programmed to
be a general purpose output.
During Reset: High After Reset: High During POS: High/GPO 
						

							Major Chips Description2-15Table 2-282371AB Pin DescriptionsNameTypeDescriptionXOE#/
GPO23O
X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output
enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data
bus, SD[7:0].  XOE# is asserted anytime a PIIX4 supported X-Bus device is
decoded, and the devices decode is enabled in the X-Bus Chip Select Enable
Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B
(PCCS0#) and Device Resource C (PCCS1#). XOE# is asserted from the falling
edge of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master
and ISA master-initiated cycles. XOE# is negated from the rising edge of the ISA
command signals for PCI Master initiated cycles and the SA[16:0] and LA[23:17]
address for ISA master-initiated cycles. XOE# is not generated during any
access to an X-Bus peripheral in which its decode space has been disabled.  If
an X-Bus not used, then this signal can be programmed to be a general purpose
output.
During Reset: High After Reset: High During POS: High/GPODMA SIGNALSDACK[0,1,2,3]
#
DACK[5,6,7]#O
DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for
DMA service has been granted by PIIX4 or that a 16-bit master has been
granted the bus. The active level (high or low) is programmed via the DMA
Command Register. These lines should be used to decode the DMA slave device
with the IOR# or IOW# line to indicate selection. If used to signal acceptance of
a bus master request, this signal indicates when it is legal to assert MASTER#. If
the DREQ goes inactive prior to DACK# being asserted, the DACK# signal will
not be asserted.
During Reset: High After Reset: High During POS: HighDREQ[0,1,2,3]
DREQ[5,6,7]I
DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4’s
DMA controller or for a 16-bit master to gain control of the ISA expansion bus.
The active level (high or low) is programmed via the DMA Command Register.
All inactive to active edges of DREQ are assumed to be asynchronous. The
request must remain active until the appropriate DACKx# signal is asserted.REQ[A:C]#/
GPI[2:4]I
PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI
protocol. They are used by a PCI agent to request DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.  If
the PC/PCI request is not needed, these pins can be used as general-purpose
inputs.GNT[A:C]#/
GPO[9:11]O
PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI
protocol. They are used by a PIIX4 to acknowledge DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.  If
the PC/PCI request is not needed, these pins can be used as general-purpose
outputs.
During Reset: High After Reset: High During POS: High/GPOTCO
TERMINAL COUNT. PIIX4 asserts TC to DMA slaves as a terminal count
indicator. PIIX4 asserts TC after a new address has been output, if the byte
count expires with that transfer. TC remains asserted until AEN is negated,
unless AEN is negated during an autoinitialization. TC is negated before AEN is
negated during an autoinitialization.
During Reset: Low After Reset: Low During POS: Low 
						

							2-16Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionINTERRUPT CONTROLLER/APIC SIGNALSAPICACK#/
GPO12O
APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after
its internal buffers are flushed in response to the APICREQ# signal. When the
I/O APIC samples this signal asserted it knows that PIIX4’s buffers are flushed
and that it can proceed to send the APIC interrupt. The APICACK# output is
synchronous to PCICLK.  If the external APIC is not used, then this is a general-
purpose output.
During Reset: High After Reset: High During POS: High/GPOAPICCS#/
GPO13O
APIC CHIP SELECT. This active low output signal is asserted when the APIC
Chip Select is enabled and a PCI originated cycle is positively decoded within
the programmed I/O APIC address space.  If the external APIC is not used, this
pin is a general-purpose output.
During Reset: High After Reset: High During POS: High/GPOAPICREQ#/
GPI5I
APIC REQUEST. This active low input signal is asserted by an external APIC
device prior to sending an interrupt over the APIC serial bus. When PIIX4
samples this pin active it will flush its F-type DMA buffers pointing towards PCI.
Once the buffers are flushed, PIIX4 asserts APICACK# which indicates to the
external APIC that it can proceed to send the APIC interrupt. The APICREQ#
input must be synchronous to PCICLK.  If the external APIC is not used, this pin
is a general-purpose input.INTROD
INTERRUPT. See CPU Interface Signals.IRQ0/
GPO14O
INTERRUPT REQUEST 0. This output reflects the state of the internal IRQ0
signal from the system timer.  If the external APIC is not used, this pin is a
general-purpose output.
During Reset: Low After Reset: Low During POS: IRQ0/GPOIRQ1I
INTERRUPT REQUEST 1. IRQ1 is always edge triggered and can not be
modified by software to level sensitive. A low to high transition on IRQ1 is
latched by PIIX4.  IRQ1 must remain asserted until after the interrupt is
acknowledged. If the input goes inactive before this time, a default IRQ7 is
reported in response to the interrupt acknowledge cycle.IRQ 3:7, 9:11,
14:15I
INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both
system board components and ISA Bus I/O devices with a mechanism for
asynchronously interrupting the CPU. These interrupts may be programmed for
either an edge sensitive or a high level sensitive assertion mode. Edge sensitive
is the default configuration.  An active IRQ input must remain asserted until after
the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.IRQ8#/
GPI6I/O
IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be
modified by software.  IRQ8# must remain asserted until after the interrupt is
acknowledged. If the input goes inactive before this time, a default IRQ7 is
reported in response to the interrupt acknowledge cycle.  If using the internal
RTC, then this can be programmed as a general-purpose input. enabling an
APIC, this signal becomes an output and must not be programmed as a general
purpose input.IRQ9OUT#/
GPO29O
IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus
interrupts out of the PIIX4 for connection to an external IO APIC. If APIC is
disabled, this signal pin is a General Purpose Output.
During Reset: High After Reset: High During POS: IRQ9OUT#/GPO 
						

							Major Chips Description2-17Table 2-282371AB Pin DescriptionsNameTypeDescriptionIRQ 12/MI
INTERRUPT REQUEST 12. In addition to providing the standard interrupt
function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can
also be programmed to provide the mouse interrupt function.  When the mouse
interrupt function is selected, a low to high transition on this signal is latched by
PIIX4 and an INTR is generated to the CPU as IRQ12. An internal IRQ12
interrupt continues to be generated until a Reset or an I/O read access to
address 60h (falling edge of IOR#) is detected.PIRQ[A:D]#I/OD
PCIPROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active
low, level sensitive, shareable interrupt inputs. They can be individually steered
to ISA interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as its
output signal.SERIRQ/
GPI7I/O
SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in
conjunction with the Distributed DMA protocol.  If not using serial interrupts, this
pin can be used as a general-purpose input.CPU INTERFACE SIGNALSA20M#OD
ADDRESS 20 MASK. PIIX4 asserts A20M# to the CPU based on combination of
Port 92 Register, bit 1 (FAST_A20), and A20GATE input signal.
During Reset: High-Z After Reset: High-Z During POS: High-ZCPURSTOD
CPU RESET. PIIX4 asserts CPURST to reset the CPU. PIIX4 asserts CPURST
during power-up and when a hard reset sequence is initiated through the RC
register.  CPURST is driven inactive a minimum of 2 ms after PWROK is driven
active. CPURST is driven active for a minimum of 2 ms when initiated through
the RC register. The inactive edge of CPURST is driven synchronously to the
rising edge of PCICLK. If a hard reset is initiated through the RC register, PIIX4
resets its internal registers (in both core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II
processor as determined by CONFIG1 signal.  For values During Reset, After
Reset, and During POS, see the Suspend/Resume and Resume Control
Signaling section.FERR#I
NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal
supporting coprocessor errors. This signal is tied to the coprocessor error signal
on the CPU. If FERR# is asserted, PIIX4 generates an internal IRQ13 to its
interrupt controller unit.  PIIX4 then asserts the INT output to the CPU. FERR# is
also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to
the CPU unless FERR# is active.IGNNE#OD
IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore
numeric exception pin on the CPU. IGNNE# is only used if the PIIX4
coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the
IGNNE# to be asserted.  IGNNE# remains asserted until FERR# is negated. If
FERR# is not asserted when the Coprocessor Error Register is written, the
IGNNE# signal is not asserted.
During Reset: High-Z After Reset: High-Z During POS: High-Z 
						

							2-18Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionINITOD
INITIALIZATION. INIT is asserted in response to any one of the following
conditions.  When the System Reset bit in the Reset Control Register is reset to
0 and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by
asserting INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded
on the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h,
bit 0. When asserted, INIT remains asserted for approximately 64 PCI clocks
before being negated.  This signal is active high for Pentium processor and
active-low for Pentium II processor as determined by CONFIG1 signal.
Pentium Processor:
During Reset: Low After Reset: Low During POS: Low
Pentium II Processor:
During Reset: High After Reset: High During POS: HighINTROD
CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an interrupt
request is pending and needs to be serviced. It is asynchronous with respect to
SYSCLK or PCICLK and is always an output. The interrupt controller must be
programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low After Reset: Low During POS: LowNMIOD
NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to
the CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is asserted,
depending on how the NMI Status and Control Register is programmed. The
CPU detects an NMI when it detects a rising edge on NMI. After the NMI
interrupt routine processes the interrupt, the NMI status bits in the NMI Status
and Control Register are cleared by software. The NMI interrupt routine must
read this register to determine the source of the interrupt. The NMI is reset by
setting the corresponding NMI source enable/disable bit in the NMI Status and
Control Register. To enable NMI interrupts, the two NMI enable/disable bits in
the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable
and Real Time Clock Address Register must be set to 0. Upon PCIRST#, this
signal is driven low.
During Reset: Low After Reset: Low During POS: LowSLP#OD
SLEEP. This signal is output to the Pentium II processor in order to put it into
Sleep state. For Pentium processor it is a No Connect.
During Reset: High-Z After Reset: High-Z During POS: High-ZSMI#OD
SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous
output that is asserted by PIIX4 in response to one of many enabled hardware or
software events.  The CPU recognizes the falling edge of SMI# as the highest
priority interrupt in the system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z After Reset: High-Z During POS: High-ZSTPCLK#OD
STOP CLOCK. STPCLK# is an active low synchronous output that is asserted
by PIIX4 in response to one of many hardware or software events. STPCLK#
connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z After Reset: High-Z During POS: High-ZCLOCKING SIGNALSCLK48I
48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This
signal may be stopped during suspend modes. 
						

							Major Chips Description2-19Table 2-282371AB Pin DescriptionsNameTypeDescriptionPCICLKI
FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK
provides timing for all transactions on the PCI Bus. All other PCI signals are
sampled on the rising edge of PCICLK, and all timing parameters are defined
with respect to this edge. Because many of the circuits in PIIX4 run off the PCI
clock, this signal MUST be kept active, even if the PCI bus clock is not active.OSCI
14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This clock
signal may be stopped during suspend modes.RTCX1,
RTCX2I/O
RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal.
External capacitors are required. These clock inputs are required even if the
internal RTC is not being used.SUSCLKO
SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI bridge
used for maintenance of DRAM refresh. This signal is stopped during Suspend-
to-Disk and Soft Off modes. For values During Reset, After Reset, and During
POS, see the Suspend/Resume and Resume Control Signaling section.SYSCLKO
ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It drives
the ISA bus directly. The SYSCLK is generated by dividing PCICLK by 4. The
SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI accesses to
the ISA bus, SYSCLK may be stretched low to synchronize BALE falling to the
rising edge of SYSCLK.
During Reset: Running After Reset: Running During POS: LowIDE SIGNALSPDA[2:0]O
PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either the
ATA command block or control block is being addressed.  If the IDE signals are
configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Primary IDE connector.  If the IDE signals are
configured for Primary 0 and Primary 1, these signals are used for the Primary 0
connector.
During Reset: High-Z After Reset: Undefined During POS: PDAPDCS1#O
PRIMARY DISK CHIP SELECT FOR 1F0H-1F7H RANGE. For ATA command
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Primary IDE
connector.  If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: HighPDCS3#O
PRIMARY DISK CHIP SELECT FOR 3F0-3F7 RANGE. For ATA control register
block.  If the IDE signals are configured for Primary and Secondary, this output
signal is connected to the corresponding signal on the Primary IDE connector.  If
the IDE signals are configured for Primary Master and Primary Slave, this signal
is used for the Primary Master connector.
During Reset: High After Reset: High During POS: HighPDD[15:0]I/O
PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or from
the IDE device. If the IDE signals are configured for Primary and Secondary,
these signals are connected to the corresponding signals on the Primary IDE
connector.  If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.
During Reset: High-Z After Reset: Undefined During POS: PDD 
						

							2-20Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionPDDACK#O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices
that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA
data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function. It is not associated with any AT compatible DMA channel.  If the
IDE signals are configured for Primary and Secondary, this signal is connected
to the corresponding signal on the Primary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the
Primary Master connector.
During Reset: High After Reset: High During POS: HighPDDREQI
PRIMARY DISK DMA REQUEST. This input signal is directly driven from the
IDE device DMARQ signal. It is asserted by the IDE device to request a data
transfer, and used in conjunction with the PCI bus master IDE function. It is not
associated with any AT compatible DMA channel.  If the IDE signals are
configured for Primary and Secondary, this signal is connected to the
corresponding signal on the Primary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the
Primary Master connector.PDIOR#O
PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device
that it may drive data onto the PDD[15:0] lines. Data is latched by PIIX4 on the
negation edge of PDIOR#. The IDE device is selected either by the ATA register
file chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA
slave arbitration signals (PDDACK#).  In an Ultra DMA/33 read cycle, this signal
is used as DMARDY# which is negated by the PIIX4 to pause Ultra DMA/33
transfers. In an Ultra DMA/33 write cycle, this signal is used as the STROBE
signal, with the drive latching data on rising and falling edges of STROBE.  If the
IDE signals are configured for Primary and Secondary, this signal is connected
to the corresponding signal on the Primary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the
Primary Master connector.
During Reset: High After Reset: High During POS: HighPDIOW#O
PRIMARY DISK IO WRITE. In normal IDE mode, this is the command to the
IDE device that it may latch data from the PDD[15:0] lines. Data is latched by
the IDE device on the negation edge of PDIOW#. The IDE device is selected
either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA[2:0]
lines, or the IDE DMA slave arbitration signals (PDDACK#).  For Ultra DMA/33
mode, this signal is used as the STOP signal, which is used to terminate an
Ultra DMA/33 transaction. If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the Primary
IDE connector.  If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.
During Reset: High After Reset: High During POS: High-Z 
						

							Major Chips Description2-21Table 2-282371AB Pin DescriptionsNameTypeDescriptionPIORDYI
PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is
directly driven by the corresponding IDE device IORDY signal.  In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data
on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this
signal is used as the DMARDY# signal which is negated by the drive to pause
Ultra DMA/33 transfers.  If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the Primary
IDE connector.  If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector.  This is a Schmitt
triggered input.SDA[2:0]O
SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either
the ATA command block or control block is being addressed. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Secondary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, these signals are used for the
Primary Slave connector.
During Reset: High-Z After Reset: Undefined During POS: SDASDCS1#O
SECONDARY CHIP SELECT FOR 170H-177H RANGE. For ATA command
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Secondary IDE
connector.  If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: HighSDCS3#O
SECONDARY CHIP SELECT FOR 370H-377H RANGE. For ATA control
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Secondary IDE
connector.  If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: High-ZSDD[15:0]I/O
SECONDARY DISK DATA[15:0]. These signals are used to transfer data to or
from the IDE device. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the
Secondary IDE connector.  If the IDE signals are configured for Primary Master
and Primary Slave, these signals are used for the Primary Slave connector.
During Reset: High-Z After Reset: Undefined During POS: SDDSDDACK#O
SECONDARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices
that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a DMA
data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function. It is not associated with any AT compatible DMA channel.  If the
IDE signals are configured for Primary and Secondary, this signal is connected
to the corresponding signal on the Secondary IDE connector.  If the IDE signals
are configured for Primary Master and Primary Slave, these signals are used for
the Primary Slave connector.
During Reset: High After Reset: High During POS: High 
						

							2-22Service GuideTable 2-282371AB Pin DescriptionsNameTypeDescriptionSDDREQI
SECONDARY DISK DMA REQUEST. This input signal is directly driven from
the IDE device DMARQ signal. It is asserted by the IDE device to request a data
transfer, and used in conjunction with the PCI bus master IDE function. It is not
associated with any AT compatible DMA channel.  If the IDE signals are
configured for Primary and Secondary, this signal is connected to the
corresponding signal on the Secondary IDE connector.  If the IDE signals are
configured for Primary Master and Primary Slave, these signals are used for the
Primary Slave connector.SDIOR#O
SECONDARY DISK IO READ. In normal IDE mode, this is the command to the
IDE device that it may drive data onto the SDD[15:0] lines. Data is latched by the
PIIX4 on the negation edge of SDIOR#. The IDE device is selected either by the
ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the
IDE DMA slave arbitration signals (SDDACK#).  In an Ultra DMA/33 read cycle,
this signal is used as DMARDY# which is negated by the PIIX4 to pause Ultra
DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the
STROBE signal, with the drive latching data on rising and falling edges of
STROBE.  If the IDE signals are configured for Primary and Secondary, this
signal is connected to the corresponding signal on the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these
signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: HighSDIOW#O
SECONDARY DISK IO WRITE. In normal IDE mode, this is the command to the
IDE device that it may latch data from the SDD[15:0] lines. Data is latched by
the IDE device on the negation edge of SDIOW#. The IDE device is selected
either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0]
lines, or the IDE DMA slave arbitration signals (SDDACK#).  In read and write
cycles this signal is used as the STOP signal, which is used to terminate an
Ultra DMA/33 transaction.  If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the
Secondary IDE connector.  If the IDE signals are configured for Primary Master
and Primary Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: HighSIORDYI
SECONDARY IO CHANNEL READY. In normal IDE mode, this input signal is
directly driven by the corresponding IDE device IORDY signal.  In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data
on rising and falling edges of STROBE. In an Ultra DMA write cycle, this signal
is used as the DMARDY# signal which is negated by the drive to pause Ultra
DMA/33 transfers.  If the IDE signals are configured for Primary and Secondary,
this signal is connected to the corresponding signal on the Secondary IDE
connector.  If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector.  This is a Schmitt
triggered input.Note: After reset, all undefined signals on the primary channel will default to the same values as the
undefined signals on the secondary channel.UNIVERSAL SERIAL BUS SIGNALSOC[1:0]#I
OVER CURRENT DETECT. These signals are used to monitor the status of the
USB power supply lines. The corresponding USB port is disabled when its over
current signal is asserted.