Acer Travelmate 7100 Service Guide
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Major Chips Description2-33Table 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription83XCKENI External Clock Enable This pin is used to select between internally synthesized clocks or externally supplied clocks. A low level on the pin selects internal mode and a high level selects external mode. In the external clock mode, the internal clock synthesizers will be disabled completely. Both PVCLK and PMCLK pins should be driven with the desired clock rates in external mode. This pin should be driven all the time during normal operation86PMCLKI/ SRATUS4/ PNLCKII/O T/SMemory Clock This pin is used for feeding external memory clock or observing internal memory clock. When in internal clock mode(XCKEN=0), the internal memory clock can be brought out using this pin. When in external clock mode (XCKEN=1), PMCLKI should be driven from an external memory clock source. General purpose Status bit 4 can be read from register CR27 bit 1(GR17 bit 0 defines the function of this pin). GR17 bit 7 enables the Modulated Clock Input function(PNLCKI) from the Spread Spectrum Clock Generator85PVCLKI/ STATUS3/ PNLCKOI/O T/SVideo Clock This pin is used for feeding external video clock or observing internal video clock. When in internal clock mode (XCKEN=0), the internal video clock can be brought out using this pin. When in external clock mode(XCKEN=1). PVCLKI should be driven from an external video clock source. General purpose Status bit 3 can be read from register CR27 bit 2. (GR17 bit 1 defines the function of this pin). GR17 bit 7 enables the Reference clock output function(PNCLKO) to the Spread Spectrum Clock GeneratorPanel Interface112FLMO First Line Marker This signal indicates start of a frame. For STN panels this pin is connected to FLM pin. For TFT panels this pin is connected to the VSYNC pin113LPO Line Pulse This signal indicates start of a line. For STN panels this pin is connected to the CP1 pin. For TFT panels this pin is connected to the HSYNC pin141SCLKO Shift Clock This signal is used to drive the panel shift clock. Some panel manufactures call this CP2115SCLKIO Shift Clocki This signal is used to drive the panel shift clock or as a General Purpose Output Pin. This clock is used for panels which use two clocks, one for the upper panel and the other for the lower panel. This pin is also configured as a General Purpose Output Pin as defined in register CR2F bits 1&0, to control the IMI chip for reduced EMI111FPHDE/ MODO Panel horizontal Display Enable/MOD This signal indicates the horizontal display time to the panels. For some panels it is used to drive the shift clock enable pin. This pin can also be configured to drive FPHDE for certain types of TFT panels which require separate horizontal display time indicator. Modulation This signal is used to drive the panel MOD or AC input142FPVCCO Flat Panel VCC This is used to control the logic power to the panels
2-34Service GuideTable 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription143FPVEEO Flat Panel VEE This is used to control the bias power to the panels108FPBACKO Flat Panel Backlight This is used to control the backlight power to the panels or as a General Purpose Output Pin as defined by register CR2F bits 3&27 6 5 4 3 2 176 174 172 171 170 169 18 17 16 15 14 13 117 118 119 120 121 122 123 124 126 127 128 129 130 131 135 137 139 140PDATA35 PDATA34 PDATA33 PDATA32 PDATA31 PDATA30 PDATA29 PDATA28 PDATA27 PDATA26 PDATA25 PDATA24 PDATA23 PDATA22 PDATA21 PDATA20 PDATA19 PDATA18 PDATA17/ LCD_ID0 PDATA16/ LCD_ID1 PDATA15/ LCD_ID2 PDATA14/ LCD_ID3 PDATA13 PDATA12 PDATA11 PDATA10 PDATA9 PDATA8 PDATA7 PDATA6 PDATA5 PDATA4 PDATA3 PDATA2 PDATA1 PDATA0O I/O I/O I/O I/OPanel data These pins are used to provide the data interface to different kinds of panels. The following table shows the functions of these pins based on the selected panel type LCD_ID[3..0] pins are general purpose read only bits which can be used for panel identification. During RESET# these LCD_ID pins are inputs. The state of these bits are reflected in register CR2Eh bits 3:0. The state of these bit can also be sampled anytime on-the-fly through register GR17 bit-3. Internally these pins are pulled-up, recommended external pull down resistor value is 22k ohmCRT Interface90VSYNCO T/SCRT Vertical Sync This output is the vertical synchronization pulse for the CRT monitor89HSYNCO T/SCRT Horizontal sync This output is the horizontal synchronization pulse for the CRT monitor
Major Chips Description2-35Table 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription98RO (Analog )RED This DAC analog output drives the CRT interface97GO (Analog )GREEN This DAC analog output drives the CRT interface96BO (Analog )BLUE This DAC analog output drives the CRT interface101REXTI (Analog )DAC Current reference This pin is used as a current reference by the internal DAC. Please refer to the NM2160 system schematics for the external circuitTV interface79CSYNCO T/SComposite Sync This output is the composite synchronization signal for RGB-to-NTSC or PAL/SECAM External Analog Encoders74NTSC_PALO T/SNTSC/PAL/SECAM Encoding Selection This pin is used to select the mode NTSC or PAL/SECAM in which the external analog encoder need to be driven147FSCO Sub-Carrier Frequency Selection This pin provides an appropriate Sub-carrier frequency 1xfsc or 4xfsc to an external NTSC or PAL/SECAM analog encoder98RO (Analog )RED This DAC analog video red component output is to drive the external RGB-to-NTSC or PAL/SECAM analog encoders97GO (Analog )GREEN This DAC analog video green component output is to drive the external RGB-to-NTSC or PAL/SECAM analog encoders96BO (Analog )BLUE This DAC analog video blue component is to drive the external RGB-to-NTSC or PAL/SECAM analog encoders externalPower Management76Standby/ Status1I/O Standby/Status1 The direction of the pin is controlled by GR18 bit 3. In output mode, this pin indicates the state of standby mode. The state of this pin is reflected in register CR25 bit 5 and can be used as a status pin77SuspendI/O Suspend This pin can be configured as control Suspend input or status Suspend output. The active high input mode is used for controlling hardware Suspend. When asserted NM2160 is forced into suspend mode where all the inputs are disabled and chip goes into the low power mode NM2160 will come out of suspend only by de-asserting this pin77SuspendI/ODuring output mode, this pin will indicate the software suspend status
2-36Service GuideTable 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription75ActivityI/O Activity This pin when in input mode and asserted indicates the system activity. A high on this pin can be used to reset internal timers. This pin when in output mode is a General Purpose Output pin as defined by CR2F bits 5&4, which can be used to control the IMI chip for reduced EMI82RTC32K/ Status2I/O Real Time Clock 32Khz/Status2 This pin is used to feed 32 kHz from an external source. It is used to generate the refresh timing for the internal display memory during Standby and software Suspend modes. 14 MHz can be used to generate the memory refresh timing in above modes. / General purpose Status bit 3, can be read from register CR27 bit 0ZV Interface167 166 165 164 163 162 161 160UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0I Chrominance Data 7:0 These are the 8-bits of chrominance data that are input to the ZV port of NM2160159 158 155 152 151 150 149 148Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0I Luminance Data 7:0 These are the 8-bits of luminance data that are input to the ZV port of NM2160144HREFI Horizontal Synchronization Pulse: This input signal provides the horizontal synchronization pulse to the ZV port168PCLKI Video Clock This signal is used to clock the valid video data and the HREF signal into the ZV Port. The maximum rate is 16 MHz. During display time, rising edge of PCLK is used to clock the 16- bit pixel data into the ZV Port146VSI Vertical SYNC This signal supplies the Vertical synchronization pulse to the ZV Port of NM2160Miscellaneous Pins87MTEST#I Memory test This active low signal is used for internal memory testing. This should be tied high for normal system operation145CLKRUN#I/O O/DClockrun The master device will control this signal to the NM2160, according to the Mobile computing PCI design guide. If this signal is sampled high by the NM2160 and the PCI clock related functions are not completed then it will drive this signal Low to request the Central Clock Resource for the continuation of the PCI clock. This function can be Enabled/Disabled through reg. GR12 bit 5
Major Chips Description2-37Table 2-3NM2160 Pin DescriptionsPin nameNumberI/ODescription110VGADISI VGA Disable This pin when active disables all the accesses to the NM2160 controller, but maintains all the screen refreshes. GR12 bit-4 enables/disables this feature. NOTE: When driven by an external source, the swing on this pin should not be above LVDD11DDC2BDI/O O/DDDC Data pin12DDC2BCI/O O/DDDC Clock pinPower pins10, 29, 44, 59, 80, 114, 125, 138, 153VSSPHost bus interface ground, ZV interface ground and Panel Interface ground23, 64, 109, 88GNDLogic ground136, 154, 173DVSSDRAM ground105AVSSMAnalog ground for MCLK synthesizer104AVSSVAnalog ground for VCLK synthesizer99AVSSR1Analog ground for DAC100AVSSR2Analog ground for DAC current reference91AVSSX1Analog ground for crystal oscillator25, 42, 57, 78HVDD Host bus interface VDD.(+5v or +3v) Includes the PCI, VL, CRT, Power management, External clock pins(PMCLKI and PVCLKI) and Miscellaneous pins27,62,107VDDLogic VDD(+3V only)134, 156, 175DVDDDRAM VDD(+3V only)116, 132, 1, 8LVDDPanel VDD(+5v or +3v)157MMVDDZV Port VDD(+5V /+3V)106AVDDMAnalog VDD for MCLK synthesizer(+3V only)103AVDDVAnalog VDD for VCLK synthesizer(+3V only)95AVDDR1Analog VDD for DAC(+3V only)102AVDDR2Analog VDD for DAC current reference(+3V only)94AVDDX1 Analog VDD for crystal oscillator. If external 14 MHz source is used AVDDX1 can be +5V or +3V based on the XTAL1 clock source levels133VBBA capacitor across ground to this pin is required. Please refer to NM2160 system schematics for more details
2-38Service Guide2.4 NMA1 NMA1 is a single audio chip that integrates OPL3 FM and its DAC, 16bit Sigma-delta CODEC, MPU401 MIDI interface, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16bit address decode, more IRQs and DMAs in compliance with PC’96. This LSI also supports the expandability, i.e. Zoomed Video and Modem interface in a Plug and Play manner, and power management(power down, power save, partial power down, and suspend/resume) that is indispensable with power-conscious application. 2.4.1 Features · Built-in OPL3 FM Synthesizer · Supports Sound Blaster Game compatibility · Supports Windows Sound System compatibility · Supports Plug&Play ISA 1.0a compatibility · Full Duplex operation · Built-in MPU401 Compatible MIDI I/O port · Built-in the 3D enhanced controller including all the analog components, Supports 16-bit addresss decode, Port for external Wavetable synthesizer · Hardware and software master volume control · Supports monaural input · 24 mA TTL bus drive capability · Supports Power Management(power down, power save, partial power down, and suspend/resume) · +5V/+3.3V power supply for digital, 5V power supply for analog · 100 pin SQFP package
Major Chips Description2-392.4.2 Block DiagramFigure 2-4NMA1 Block Diagram
2-40Service Guide2.4.3 Pin DiagramFigure 2-5NMA1 Pin Diagram
Major Chips Description2-412.4.4 Pin Descriptions Conventions used in the pin description types: I+:Input Pin with Pull up Resistor T:TTL-tri-state output pin Schmitt:TTL-Schmitt input pin O+:Output Pin with Pull up Resistor Table 2-4NMA1 Pin DescriptionsPin nameNumberI/ODescriptionISA bus interface: 36 pinsD7-08I/OData BusA15-012IAddress BusAEN1IAddress Bus Enable/IOW1IWrite Enable/IOR1IRead EnableRESET1IResetIRQ3,5,7,9,10,116TInterrupt requestDRQ0,1,33TDMA Request/DACK0,1,33IDMA AcknowledgeAnalog Input&Output: 24 pinsOUTL1OLeft mixed analog outputOUTR1ORight mixed analog outputVREFI1IVoltage reference inputVREFO1OVoltage reference outputAUX1L1ILeft AUX1 inputAUX1R1IRight AUX1 inputAUX2L1ILeft AUX2 inputAUX2R1IRight AUX2 inputLINEL1ILeft LINE inputLINER1IRight LINE inputMIC1IMIC inputMIN1IMonaural inputTRECL1Left Treble capacitorTRECR1Right Treble capacitorSBFLTL1Left SBDAC filterSBFLTR1Right SBDAC filterSYNSHL1Left SYNDAC sample/ hold capacitorSYNSHR1Right SYNDAC sample/ hold capacitorADFLTL1Left input filter
2-42Service GuideTable 2-4NMA1 Pin DescriptionsPin nameNumberI/ODescriptionADFLTR1Right input filterVOCOL1OLeft voice outputVOCOR1ORight voice outputVOCIL1ILeft voice inputVOCIR1IRight voice inputMiscellaneous pins: 14 pinsSYEN1IExternal synthesizer enable inputSYCS1OExternal synthesizer chip select outputSYCLK1IExternal synthesizer clock input or ZV clock inputSYLR1IExternal synthesizer L/R clock input or ZV L/R clock inputSYIN1IExternal synthesizer data input or ZV data inputSYCLKO1OExternal synthesizer master clock outputRSVD8Reserved for future useOthers: 27 pinsRXD1I+MIDI Data ReceiveTXD1OMIDI Data Transfer/VOLUP1I+Hardware Volume(Up)/VOLDW1I+Hardware Volume(Down)X33I1I33.8688MHZX33O1O33.8688MHZX24I1I24.576MHZX24O1O24.576MHZAVDD2Analog Power Supply(put on +5.0V)DVDD3Digital Power Supply(put on +5.0V or +3.3V)AVSS2Analog GNDDVSS7Digital GND