Acer Travelmate 7100 Service Guide

							Major Chips Description2-53Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/CTS1,
/CTS272, 64I
UARTs Clear to Send.  When low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal is a modem
status input.  The CPU tests the condition of this /CTS signal by
reading bit 4 (CTS) of the Modem Status Register (MSR) for the
appropriate serial channel.  Bit 4 is the complement of the CTS signal.
Bit 0 (DCTS) has no effect on the transmitter.
/CTS2 is multiplexed with A13.  When it is not selected, it is masked to
“0”.
NOTE: Whenever the MSR DCTS bit is set, an interrupt is generated if
Modem Status interrupts are enabled.D7-D010-17I/O
Data.  These are bidirectional data lines to the microprocessor.  D0 is
the LSB and D7 is the MSB.  These signals have a 24 mA (sink)
buffered outputs./DACK0
/DACK1
/DACK2
/DACK353,
52,
3
49I
DMA Acknowledge 0, 1, 2, 3.  These active low inputs acknowledge
the DMA request and enable the /RD and /WR inputs during a DMA
transfer. It can be used by one of the following: FDC or Parallel Port.
If none of them uses this input pin, it is ignored.  If the device which
uses on of this pins is disabled or configured with no DMA, this pin is
also ignored.
DACK3 is multiplexed with DRATE1, MSEN1, /CS0 and SIRQI2./DCD1, /DCD275, 67I
UARTs Data Carrier Detect.  When low, this indicates that the
modem or data set has detected the data carrier.  The /DCD signal is
a modem status input.  The CPU tests the condition of this /DCD
signal by reading bit 7 (DCD) of the Modem Status Register (MSR) for
the appropriate serial channel.  Bit 7 is the complement of the DCD
signal.  Bit 3 (DDCD) of the MSR indicates whether DCD input has
changed state since the previous reading of the MSR.
NOTE: Whenever the MSR DDCD bit is set, an interrupt is generated if
Modem Status interrupts are enabled.DENSEL
(Normal Mode)46O
FDC Density Select.  DENSEL indicates that a high FDC density data
rate (500 Kbs, 1 Mbs or 2 Mbs) or a low density data rate (250 or 300
Kbs) is selected.  DENSEL is active high for high density (5.25-inch
drives) when IDENT is high, and active low for high density (3.5-inch
drives) when IDENT is low.  DENSEL is also programmable via the
Mode command.DENSEL
(PPM Mode)76O
FDC Density Select.  This pin offers an additional Density Select
signal in PPM Mode when PNF=0./DIR
(Normal Mode)39O
FDC Direction.  This output determines the direction of the floppy disk
drive (FDD) head movement (active = step-in; inactive = step-out)
during a seek operation.  During reads or writes, DIR is inactive./DIR
(PPM Mode)78O
FDC Direction.  This pin offers an additional Direction signal in PPM
Mode when PNF = 0./DR0,
/DR1
(Normal Mode)42, 43O
FDC Drive Select 0, 1.  These are the decoded drive select outputs
that are controlled by Digital Output Register bits D0, D1.  The Drive
Select outputs are gated with DOR bits 4-7.  These are active low
outputs.  They are encoded with information to control four FDDs
when bit 4 of the Function Enable Register (FER) is set.  DR0
exchanges logical drive values with DR1 when bit 4 of Function
Control Register is set. 
						

							2-54Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/DR1
(PPM Mode)83O
FDC Drive Select 1.  This pin offers an additional Drive Select signal
in PPM Mode when PNF = 0.  It is drive select 1 when bit 4 of FCR is
0.  It is drive select 0 when bit 4 of FCR is 1.  This signal is active low./DR2347O
FDC Drive 2 or 3.  /DR23 is asserted when either Drive 2 or Drive 3 is
assessed(except during logical drive exchange)./DRATE0
/DRATE1
(Normal Mode)50, 49O
FDC Data Rate 0, 1.  These outputs reflect the currently selected FDC
data rate (bits 0 and 1 in the Configuration Control Register (CCR) or
the Data Rate Select Register (DSR), whichever was written to last).
The pins are totem-pole buffered outputs (6 mA sink, 6 mA source)./DRATE0
(PPM Mode)85O
FDC Data Rate 0.  This pin provides an additional Data Rate signal, in
PPM mode, When PNF=0.DRQ0
DRQ1
DRQ2
DRQ354
31
2
58O
DMA Request 0, 1, 2.   \An active high output that signals the DMA
controller that a data transfer is required.  This DMA request can be
sourced by one of the following: FDC or Parallel Port.
When it is not sourced by and of them, it is in TRI-STATE.  When the
sourced device is disabled or when the sourced device is configured
with no DMA, it is also in TRI-STATE.  Upon reset, DRQ2 is used by
the FDC; DRQ0, 1, 3 are in TRI-STATE.  DRQ3 is multiplexed with
IRQ15 and SIRQI1./DRV247I
FDD Drive2.  This input indicates whether a second disk drive has
been installed.  The state of this pin is available from Status Register
A in PS/2 mode.  (See PNF for further information)./DSKCHG
(Normal Mode)30I
Disk Change.  The input indicates if the drive door has been opened.
The state of this pin is available from the Digital Input Register.  This
pin can also be configured as the RGATE data separator diagnostic
input via the Mode command./DSKCHG
(PPM Mode)87I
Disk Change.  This pin offers an additional Disk Change signal in
PPM Mode when PNF = 0./DSR1
/DSR274,
66I
UARTs Data Set Ready.  When low, this indicates that the data set or
modem is ready to establish a communications link.  The DSR signal
is a modem status input.  The CPU tests the /DSR signal by reading
bit 5 (DSR) of the Modem Status Register (MSR) for the appropriate
channel.  Bit 5 is the complement of the DSR signal.  Bit 1 (DDSR) of
the MSR indicates whether the DSR input has changed state since the
previous reading of the MSR.
NOTE:  Whenever the DDSR bit of the NSR is set, an interrupt is
generated if Modem Status interrupts are enabled./DSTRB76O
EPP Data Strobe.  This signal is used in EPP mode as data strobe.  It
is an active low signal./DTR1
/DTR269,
61O
UARTs Data Terminal Ready.  When low, this output indicates to the
modem or data set that the UART is ready to establish a
communications link.  The DTR signal can be set to an active low by
programming bit 0 (DTR) of the Modem Control Register to a high
level.  A Master Reset operation sets this signal to its inactive (high)
state.  Loop mode operation holds this signal to its inactive state./ERR77I
Parallel Port Error.  This input is set low by the printer when an error
is detected.  This pin has a nominal 25 KOHM pull-up resistor
attached to it. 
						

							Major Chips Description2-55Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/HDSEL
(Normal Mode)32O
FDC Head Select.  This output determines which side of the FDD is
accessed.  Active selects side 1, inactive selects side 0./HDSEL
(PPM Mode)77O
FDC Head Select.  This pin offers an additional Head Select signal in
PPM Mode when PNF = 0.IDLE41O
FDD IDLE.  IDLE indicates that the FDC is in the IDLE state and can
be powered down.  Whenever the FDC is in IDLE state, or in power-
down state, the pin is active high./INDEX45I
Index.  This input signals the beginning of a FDD track./INDEX
(Normal Mode)92I
Index.  This pin gives an additional Index signal in PPM mode when
PNF = 0./INIT
(PPM Mode)78I/O
Initialize.  When this signal is low, it causes the printer to be
initialized.  This pin is in a tristate condition 10 ns after a 1 is loaded
into the corresponding Control Register bit.  The system should pull
this pin high using a 4.7 KW resistor.IORCHDY51O
I/O Channel Ready.  When IORCHDY is driven low, the EPP extends
the host cycle.IRQ3, 4
IRQ5-7
IRQ9-11
IRQ12, 15
(PnP Mode)99, 98
96-94,
55-57,
66, 58I/O
Interrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15.  This pin can be a totem-
pole output or an open-drain output.  The interrupt can be sourced by
one of the following: UART1 and/or UART2, parallel port, FDC,
SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.
IRQ5 is multiplexed with ADRATE0.
IRQ12 is multiplexed with /DSR2 and IRRX2.
IRQ15 is multiplexed with SIRQI1.IRQ3, 4
(Legacy Mode)99, 98O
Interrupt 3 and 4.  These are active high interrupts associated with
the serial ports.  IRQ3 presents the signal if the serial channel has
been designated as COM2 or COM4.  IRQ4 presents the signal if the
serial port is designated as COM1 or COM3.  The interrupt is reset low
(inactive ) after the appropriate interrupt service routine is executed.IRQ5
(Legacy Mode)96I/O
Interrupt 5.  Active high output that indicates a parallel port interrupt.
When enabled, this pin follows the /ACK signal input.  When it is not
enabled, this signal is tri-state.  This pin is I/O only when ECP is
enabled, and IRQ5 is configured.IRQ6
(Legacy Mode)95O
Interrupt 6.  Active high output to signal the completion of the
execution phase for certain FDC commands.  Also used to signal
when a data transfer is ready during a non-DMA operation.IRQ7
(Legacy Mode)94I/O
Interrupt 7.  Active high output that indicates a parallel port interrupt.
When enabled, this signal follows the /ACK signal input.  When it is
not enabled, this signal is tri-state.  This pin is I/O only when ECP is
enabled, and IRQ7 is configured.IRRX1
IRRX265,
66I
Infrared Receive 1 and 2.  Infrared serial data input signals.  IRRX1
is multiplexed with SIN2.IRRX2 is multiplexed with /DSR2 and IRQ12,
and IRSL0.IRSL0,
IRSL166
6O
Infrared Control 0, 1.  These signals control the infrared Analog Front
End(AFE).  IRSEL0 is multiplexed with DSR2, IRQ12, and IRRX2.IRSL241 or
47I
Infrared Control 2.  These signals control the infrared Analog Front
End(AFE).  IRSL2 is multiplexed with either /DRV2, PNF, /DR23 and
/SIRQI13, or with /MTR1 and IDLE. 
						

							2-56Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescriptionIRTX63O
Infrared Transmit. Infrared serial data output.  Software configuration
selects either IrDA or Sharp-IR protocol.
This pin is multiplexed with SOUT2/BOUT/CFG0.MR100I
Master Reset.  Active high output that resets the controller to the idle
state and resets all disk interface outputs to their inactive states.  The
DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values.  The Specify
command parameters are not affected/MSEN0
/MSEN1
(Normal Mode)50, 49I
Media Sense.  These pins are Media Sense input pins when bit 0 of
FCR is 0.  Each pin has a 10 KW internal pull-up resistor.  When bit 0
of FCR is 1, these pins are Data Rate output pins and the pull-up
resistors are disabled./MSEN0
/MSEN1
(PPM Mode)86, 84I
Media Sense.  These pins gives additional Media Sense signals for
PPM Mode and PNF = 0./MTR0
/MTR1
(Normal Mode)44, 41O
FDC Motor Select 0, 1.  These are the motor enable lines for drives 0
and 1, and are controlled by bits D7-D4 of the Digital Output register.
They are active low outputs.  They are encoded with information to
control four FDDs when bit 4 of the Function Enable Register (FER) is
set.  MTR0 exchanges logical motor values with MTR1 when bit 4 of
FCR is set./MTR1
(PMM Mode)82O
FDC Motor Select 1.  This pin offers an additional Motor Select 1
signal in PPM mode when PNF = 0.  This pin is the motor enable line
for drive 1 when bit 4 of FCR is 0.  It is the motor enable line for drive
0 when bit 4 of FCR 1.  This signal is active lowPD43O
FDC Power Down.  This pin is PD output when bit 4 of PMC is 1.  It is
/DR1 when bit 4 of PMC is 0.  PD is active high whenever the FDC is
in power-down state, either via bit 6 of the DSR (or bit 3 of FER, or bit
0 of PTR), or via the mode command.PD0-792-89,
87-84I/O
Parallel Port Data.  These bidirectional pins transfer data to and from
the peripheral data bus and the parallel port Data Register.  These
pins have high current drive capability.PE81I
Parallel Port Paper End.  This input is set high by the printer when it
is out of paper.  This pin has a nominal 25 KW pull-down resistor
attached to it.PNF47I
Printer Not Floppy.  PNF is the Printer Not Floppy pin when bit 2 of
FCR is 1.  It selects the device which is connected to the PPM pins.  A
parallel printer is connected when PNF = 1 and a floppy disk drive is
connected when PNF = 0.  This pin is the DRV2 input pin when bit 2 of
FCR is 0./RD17I
Read.  Active low input to signal a data read by the microprocessor./RDATA
(Normal Mode)33I
FDD Read Data.  This input is the raw serial data read from the floppy
disk drive./RDATA
(PPM Mode)89I
FDD Read Data.  This pin supports an additional Read Data signal in
PPM Mode when PNF = 0. 
						

							Major Chips Description2-57Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/RI1
/RI268, 60I
UARTs Ring Indicator.  When low, this indicates that a telephone ring
signal has been received by the modem.  The /RI signal is a modem
status input whose condition is tested by the CPU by reading bit 6 (RI)
of the Modem Status Register (MSR) for the appropriate serial
channel.  Bit 6 is the complement of the RI signal.  Bit 2 ( TERI) of the
MSR indicates whether the RI input has changed from low to high
since the previous reading of the MSR.
NOTE:  When the TERI bit of the MSR is set and Modem Status
interrupts are enabled, an interrupt is generated./RTS1
/RTS272, 64O
UARTs Request to Send.  When low, this output indicates to the
modem or data set that the UART is ready to exchange data.  The
RTS signal can be set to an active low by programming bit 1 (RTS) of
the Modem Control Register to a high level.  A Master Reset operation
sets this signal to its inactive (high) state.  Loop mode operation holds
this signal to its inactive state.SIN1
SIN273, 65I
UARTs Serial Input.  This input receives composite serial data from
the communications link (peripheral device, modem, or data set).SIRQ1
SIRQ2
SIRQ458,
49,
47I
System interrupt 1, 2, and 3.  This input can be routed to one of the
following output pins: IRQ3-IRQ7, IRQ9-IRQ12.  SIRQ12 and SIRQ13
can be also routed to IRQ15.  Software configuration determines to
which output pin the input pin is routed to.
SIRQ1 is multiplexed with IRQ15, SRIQ12 is multiplexed with
DRATE1/MSEN1/CS0, and SIRQ3 is multiplexed with
DRV2/PNF/DR23.SLCT80I
Parallel Port Select.  This input is set high by the printer when it is
selected.  This pin has a nominal 25 KW pull-down resistor attached to
it./SLIN79I/O
Parallel Port Select Input.  When this signal is low, it selects the
printer.  This pin is in a tristate condition 10 ns after a 0 is loaded into
the corresponding Control Register bit.  The system should pull this
pin high using a 4.7 KW resistor.SOUT1
SOUT271,
63O
UARTs Serial Output.  This output sends composite serial data to the
communications link (peripheral device, modem, or data set).  The
SOUT signal is set to a marking state (logic 1) after a Master Reset
operation./STB93I/O
Parallel Port Data Strobe.  This output indicates to the printer that a
valid data is available at the printer port.  This pin is in a tristate
condition 10 ns after a 0 is loaded into the corresponding Control
Register bit.  The system should pull high using a 4.7 KW./STEP
(Normal Mode)38O
FDC Step.  This output signal issues pulses to the disk drive at a
software programmable rate to move the head during a seek
operation./STEP
(PPM Mode)79O
FDC Step.  This pin gives an additional step signal in PPM Mode
when PNF = 0.TC4I
Terminal Count.  Control signal from the DMA controller to indicate
the termination of a DMA transfer.  TC is accepted only when FDACK
is active.  TC is active high in PC-AT and Model 30 modes, and active
low in PS/2 mode. 
						

							2-58Service GuideTable 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescription/TRK0
(Normal Mode)35I
FDC Track 0.  This input indicates the controller that the head of the
selected floppy disk drive is at track zero./TRK0
(PPM Mode)91I
FDC Track 0.  This pin gives an additional Track 0 signal in PPM
Mode when PNF = 0.VDDB, C48, 97
Power Supply.  This is the 3.3V/5V supply voltage for the
PC87332VJG circuitry.VSSB-E40, 7,
88, 59Ground.  This is the ground for the PC87332VJG circuitry./WAIT82I
EPP Wait.  This signal is used in EPP mode by the parallel port device
to extend its access cycle.  It is an active low signal./WDATA
(Normal Mode)37O
FDC Write Data.  This output is the write precompensated serial data
that is written to the selected floppy disk drive.  Precompensation is
software selectable./WDATA
(PPM Mode)81O
FDC Write Data.  This pin provides an additional Write Data signal in
PPM Mode when PNF=0.  (See PE.)/WGATE
(Normal Mode)36O
FDC Write Gate.  This output signal enables the write circuitry of the
selected disk drive.  WGATE has been designated to prevent glitches
during power-up and power-down.  This prevents writing to the disk
when power is cycled./WGATE
(PPM Mode)80O
FDC Write Gate.  This pin gives an additional Write Gate signal in
PPM mode when PNF = 0./WP
(Normal Mode)34I
FDC Write Protect.  This input indicates that the disk in the selected
drive is write protected./WP
(PPM Mode)90I
FDC Write Protect.  This pin gives an additional Write Gate signal in
PPM mode when PNF = 0./WR16I
Write.  An active low input to signal a write from the microprocessor to
the controller./WRITE93O
EPP Write Strobe.  This signal is used in EPP mode as write strobe.
It is active low.X15I
Clock.  Active clock input signal of 14.318 MHz, 24MHz or 48MHz./ZWS1O
Zero Wait State.  This pin is the Zero Wait State open drain output pin
when bit 6 of FCR is 0.  ZWS is driven low when the EPP or ECP is
written, and the access can be shortened. 
						

							Major Chips Description2-592.7 CL-PD6832: PCI-to-CardBus Host Adapter
The CL-PD6832 is a single-chip PC Card host adapter solution capable of controlling two fully
independent CardBus sockets. The chip is compliant with PC Card Standard, PCMCIA 2.1, and
JEDIA 4.1 and is optimized for use in notebook and handheld computers where reduced form
factor and low power consumption are critical design objectives.
The CL-PD6832 chip employs energy-efficient, mixed-voltage technology that can reduce system
power consumption. The chip also provides both Hardware and Software Suspend modes, which
stop the internal clock, and an automatic Low-Power Dynamic mode, which stops the clocks on PC
Card sockets and stops internal clock distribution, thus turning off much of the system power.
The CL-PD6832 allows easy translation of incoming memory commands to PC Card-16 I/O
commands for processors with memory commands only. The CL-PD6832 enables such processors
to use PC Card I/O devices with fully programmable windows. PC applications typically access PC
Cards through the socket/card-services software interface. To assure full compatibility with existing
socket/card-services software and PC-card applications, the register set in the CL-PD6832 is a
superset of the CL-PD6729 register set. The CL-PD6729 register set is accessible through either
the memory or the I/O space.
The chip provides fully buffered PC Card interfaces, meaning that no external logic is required for
buffering signals to/from the interface, and power consumption can be controlled by limiting signal
transitions on the PC Card bus.
2.7.1 Features
· Single-chip CardBus host adapter
· Direct connection to PCI bus and two Card sockets
· Compliant with PCI 2.1, PC Card Standard, and JEDIA 4.1
· CL-PD672X-compatible register set, ExCA(TM)-compatible
· Programmable interrupt protocol: PCI, PC/PCI, External-Hardware, or PCI/Way interrupt
signalling modes
· Serial interface to power control devices
· Automatic Low-Power Dynamic mode for lowest power consumption
· Programmable Suspend mode and hardware Suspend capability
· Seven fully programmable memory or I/O windows per socket
· Programmable CardBus timing up to 33 MHz
· ATA disk interface support
· Mixed-voltage operation (3.3/5.0V)
· Supports low-voltage PC Card specification
· Socket-to-socket transfer (bus master) capability
· Programmable per-socket activity indication bits
· Pin compatible with CL-PD6730 
						

							2-60Service Guide· 208-pin PQFP
2.7.2 Pin DiagramFigure 2-10CL-PD6832 Pin Diagram
2.7.3 Pin Descriptions
The following conventions apply to the pin description tables:
· A pound sign (#) at the end of a pin name indicates an active-low signal for the PCI bus.
· A dash (-) at the beginning of a pin name indicates an active-low signal for the PCMCIA bus. 
						

							Major Chips Description2-61· An asterisk (*)  at the end of a pin name indicates an active-low signal that is a general-
interface for the CL-PD6832.
· A double-dagger superscript (‡) at the end of the pin name indicates signals that are used for
power-on configuration switches.
· The l/O-type code (I/O) column indicates the input and output configurations of the pins on the
CL-PD6832.The possible types are defined below.I/O TypeDescriptionIInput pinI-PUInput pin with internal pull-up resistorOConstant-driven output pinI/OInput/output pinO-ODOpen-drain output pinO-TSTristate output pinGNDGround pinPWRPower pin· The power-type code (Pwr.) column indicates the output drive power source for an output pin or the pull-
up power source for an input pin on the CL-PD6832. The possible types are defined below.Power TypeOutput or Pull-up Power Source1+5v: powered from a 5-volt power supply2A_SOCKET_VCC: powered from the Socket A Vcc supply connecting to PC Card
pins 17 and 51 of Socket A3
B_SOCKET_VCC: powered from the Socket B Vcc supply connecting to PC Card
pins 17 and 51 of Socket B4PCI_VCC: powered from the PCI bus power supply5CORE_VDD: powered from a 3.3-volt power supply 
						

							2-62Service GuideThe following table lists the pin descriptions
Table 2-7CL-PD6832 Pin DescriptionsPin NameDescriptionPin NumberI/OPowerPCI Bus Interface PinsAD[31:0]
PCI Bus Address Input / Data
Input/Outputs: These pins connect to PCI bus
signals AD[31:0].4-5, 7-12, 16-20,
22-24, 38-43, 45-
46, 48 49, 51-56I/O4C/BE[3:0]#
PCI Bus Command / Byte Enables: The
command signaling and byte enables are
multiplexed on the same pins. During the
address phase of a transaction, C/BE[3:0]# are
interpreted as the bus commands. During the
data phase, C/BE[3:0]# are interpreted as byte
enables. The byte enables are to be valid for
the entirety of each data phase, and they
indicate which bytes in the 32-bit data path are
to carry meaningful data for the current data
phase.13, 25, 36, 47I/OFRAME#
Cycle Frame: This signal driven by current
master indicates that a bus transaction is
beginning. While FRAME# is asserted, data
transfers continue. When FRAME# is
deasserted, the transaction is in its final phase.27I/OIRDY#
Initiator Ready: This input indicates the
initiating agents ability to complete the current
data phase of the transaction. IRDY# is used in
conjunction with TRDY#.29I/OTRDY#
Target Ready: This output indicates the target
agent’s ability to complete the current data
phase of the transaction. TRDY# is used in
conjunction with IRDY#.30I/O4STOP#
Stop: This output indicates the current target is
requesting the master to stop the current
transaction.32I/O4LOCK#Lock Transaction: This signal is used by a
PCI master to perform a locked transaction to
a target memory. LOCK# is used to prevent
more than one master from using a particular
system resource.58I/O4IDSEL
Initialization Device Select: This input is used
as a chip select during configuration read and
write transactions. This is a point-to-point
signal. The CL-PD6832 must be connected to
its own unique IDSEL line (from the PCI bus
arbiter or one of the high-order AD bus pins).15IDEVSEL#
Device Select: when actively driven, indicates
that CL-PD6832 has decoded its own PCI
address as the target of the current access. As
an input, indicates whether any device on the
bus has been selected.31I/O4