Acer Travelmate 7100 Service Guide
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Major Chips Description2-432.5 Philips 87C552 System Management Controller The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51. The 87C552 contains a 8kx8 a volatile 256x8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16- bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2 C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C552 can be expanded using standard TTL compatible memories and logic. In addition, the 87C552 has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz (24MHz) crystal, 58% of the instructions are executed in 0.75ms (0.5ms) and 40% in 1.5ms (1ms). Multiply and divide instructions require 3ms (2ms). 2.5.1 Features · 80C51 central processing unit · 8kx8 EPROM expandable externally to 64k bytes · An additional 16-bit timer/counter coupled to four capture registers and three compare registers · Two standard 16-bit timer/counters · 256x8 RAM, expandable externally to 64k bytes · Capable of producing eight synchronized, timed outputs · A 10-bit ADC with eight multiplexed analog inputs · Two 8-bit resolution, pulse width modulation outputs · Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs · I2 C-bus serial I/O port with byte oriented master and slave functions · Full-duplex UART compatible with the standard 80C51 · On-chip watchdog timer · Speed ranges: 16MHz
2-44Service Guide· Extended temperature ranges · OTP package available 2.5.2 Block DiagramFigure 2-687C552 Block Diagram
Major Chips Description2-452.5.3 Pin Diagram9 P4.2/CMSR2 8 P4.1/CMSR1 7 P4.0/CMSR0 6 EW# 5 PWM1# 4 PWM0# 3 STADC 2 VDD 1 P5.0/ADC0 68 P5.1/ADC1 67 P5.2/ADC2 66 P5.3/ADC3 65 P5.4/ADC4 64 P5.5/ADC5 63 P5.6/ADC6 62 P5.7/ADC7 61 AVDD60AVSS 59AVref+ 58AVref– 57P0.0/AD0 56P0.1/AD1 55P0.2/AD2 54P0.3/AD3 53P0.4/AD4 52P0.5/AD5 51P0.6/AD6 50P0.7/AD7 49EA#/VPP 48ALE/PROG# 47PSEN# 46P2.7/A15 45P2.6/A14 44P2.5/A13 43 P2.4/A12 42 P2.3/A11 41 P2.2/A10 40 P2.1/A09 39 P2.0/A08 38 NC 37 VSS 36 VSS 35 XTAL1 34 XTAL2 33 NC 32 NC 31 P3.7/RD 30 P3.6/WR 29 P3.5/T1 28 P3.4/T0 27 P3.3/INT1P4.3/CMSR310 P4.4/CMSR411 P4.5/CMSR512 P4.6/CMT013 P4.7/CMT114 RST15 P1.0/CT0I16 P1.1/CT1I17 P1.2/CT2I18 P1.3/CT3I19 P1.4/T220 P1.5/RT221 P1.6/SCL22 P1.7/SDA23 P3.0/RxD24 P3.1/TxD25 P3.2/INT026 Figure 2-787C552 Pin Diagram
2-46Service Guide2.5.4 Pin Descriptions Table 2-587C552 Pin DescriptionsMnemonicPin No.TypeName And FunctionVDD2I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode.STADC3I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software).PWM0#4O Pulse Width Modulation: Output 0.PWM1#5O Pulse Width Modulation: Output 1EW#6I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.P0.0-P0.757-50I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during programming and to output the code byte during verification.P1.0-P1.716-23I/O Port 1: 8-bit I/O port. Alternate functions include:16-21I/O (P1.0-P1.5): Quasi-bidirectional port pins.22-23I/O (P1.6, P1.7): Open drain port pins.16-19I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.20I T2 (P1.4): T2 event input.21I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.22I/O SCL (P1.6): Serial port clock line I 2 C-bus.23I/O SDA (P1.7): Serial port data line I 2 C-bus. Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc.P2.0-P2.739-46I/O Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on P2.4.P3.0-P3.724-31I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:24 RxD(P3.0): Serial input port.25 TxD (P3.1): Serial output port.26 INT0 (P3.2): External interrupt.27 INT1 (P3.3): External interrupt.28 T0 (P3.4): Timer 0 external input.29 T1 (P3.5): Timer 1 external input.30 WR (P3.6): External data memory write strobe.31 RD (P3.7): External data memory read strobe.
Major Chips Description2-47Table 2-587C552 Pin DescriptionsMnemonicPin No.TypeName And FunctionP4.0-P4.77-14I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:7-12O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 13, 1413, 14O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.P5.0-P5.768-62,I Port 5: 8-bit input port.1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.RST15I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.XTAL135I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used.XTAL234O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used.VSS36, 37I Digital ground.PSEN#47O Program Store Enable: Active-low read strobe to external program memory.ALE/PROG#48O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG#) during EPROM programming.EA#/V PP49I External Access: When EA# is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA# is held at TTL low level, the CPU executes out of external program memory. EA# is not allowed to float. This pin also receives the 12.75V programming supply voltage (VPP ) during EPROM programming.AVREF–58I Analog to Digital Conversion Reference Resistor: Low-end.AVREF+59I Analog to Digital Conversion Reference Resistor: High-end.AVSS60I Analog GroundAVDD61I Analog Power Supply
2-48Service Guide2.6 NS87338VJG Super I/O Controller The PC87338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super l/O family. Advanced power management features, mixed voltage operation and integrated Serial-lnfrared(both IrDA and Sharp) support makes the PC87338 an ideal choice for low-power and/or portable personal computer applications. The PC87338 FDC uses a high performance digital data separator eliminating the need for any external filter components. It is fully compatible with the PC8477 and incorporates a superset of DP8473, NEC PD765 and N82077 floppy disk controller functions. All popular 5.25” and 3.5” floppy drives, including the 2.88 MB 3.5” floppy drive, are supported. In addition, automatic media sense and 2 Mbps tape drive support are provided by the FDC. The two UARTs are fully NS16450 and NS16550 compatible. Both ports support MIDI baud rates and one port also supports IrDA 1.0 SIR(with data rate of 115.2Kbps), IrDA 1.1 MIR and FIR(with data rate of 1.152Mbps and 4.0Mbps respectively) , and Sharp SIR(with data rate of 38.4Kbps respectively) compliant signaling protocol. The parallel port is fully IEEE 1284 level 2 compatible. The SPP(Standard Parallel Port) is fully compatible wit ISA and EISA parallel ports. In addition to the SPP, EPP(Enhanced Parallel Port) and ECP(Extended Capabilities Port) modes are supported by the parallel port. A set of configuration registers are provided to control the Plug and Play and other various functions of the PC87338. These registers are accessed using two 8-bit wide index and data registers. The ISA I/O address of the register pair can be relocated using a power-up strapping option and the software configuration after power-up. When idle, advanced power management features allows the PC87338 to enter extremely low power modes under software control. The PC87338 operates at a 3.3/5V power supply. 2.6.1 Features · 100% compatible with ISA, and EISA architectures · The Floppy Disk Controller: · Software compatible with the DP8473, the 765A and the N82077 · 16-byte FlFO(disabled by default) · Burst and Non-Burst modes · Perpendicular Recording drive support · New high-performance internal digital data separator(no external filter components required) · Low-power CMOS with enhanced power-down mode · Automatic media-sense support, with full IBM TDR(Tape Drive Register) implementation · Supports fast 2 Mbps and standard 1 Mbps/500 kbps/250 kbps tape drives
Major Chips Description2-49· The Bidirectional Parallel Port: · Enhanced Parallel Port(EPP) compatible · Extended Capabilities Port(ECP) compatible, including level 2 support · Bidirectional under either software or hardware control · Compatible with ISA, and EISA, architectures · Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive(FDD) · Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage · The UARTs: · Software compatible with the PC16550A and PC16450 · MIDI baud rate support · Infrared support on UART2 (IrDA 1.0 SIR, IrDA 1.1 MIR and FIR, and Sharp SIR) · The Address Decoder · 6 bit or 10 bit decoding · External Chip Select capability when 10 bit decoding · Full relocation capability(No limitation) · Enhanced Power Management · Special configuration registers for power-down · Enhanced programmable power-down FDC command · Auto power-down and wake-up modes · 2 special pins for power management · Typical current consumption during power-down is less than 10 uA · Reduced pin leakage current · Voltage support · 3.3/5V operation · The General Purpose Pins: · 1 pin, for 2 separate programmable chip select decoders, can be programmed for game port control · Plug and Play Compatible: · 16 bit addressing(full programmable) · 10 selectable IRQs · 4 selectable DMA Channels · 3 SIRQ Inputs allows external devices to mapping IRQs · 100-Pin TQFP package - PC87338VJG
2-50Service Guide2.6.2 Block DiagramConfiguration RegistersUART (16550 or 16450)UART + IrDA/HP & Sharp IR (16550 or 16450)General Purpose RegistersPower Down LogicIEEEE1284 Parallel PortHifh Current DriverFloppy Disk Controller with Digital Data Separator (Enhabced 8477)I/O PortsControl InterruptDataHandshakeFloppy Drive Interface OSCInterrupt and DMAFloppy Drive Interface InterruptIR Interface Serial Interface Interrupt Serial Interface Config. Inputs Figure 2-8NS87338VJG Block Diagram
Major Chips Description2-512.6.3 Pin DiagramFigure 2-9NS87338VJG Pin Diagram
2-52Service Guide2.6.4 Pin Description Table 2-6NS87338VJG Pin DescriptionsPinNo.I/ODescriptionA15-A067, 64, 62-60, 29, 19- 28I Address. These address lines from the microprocessor determine which internal register is accessed. A0-A15 are dont cares during DMA transfer./ACK83I Parallel Port Acknowledge. This input is pulsed low by the printer to indicate that it has received the data from the parallel port. This pin has a nominal 25 KW pull-up resistor attached to it.ADRATE0, ADRATE196, 46O FDD Additional Data Rate 0,1. These outputs are similar to DRATE0, 1. They are provided in addition to DRATE0, 1. They reflect the currently selected FDC data rate, (bits 0 and 1 in the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last). ADRATE0 is configured when bit 0 of ASC is 1. ADRATE1 is configured when bit 4 of ASC is 1. (See IRQ5 and DENSEL for further information)./AFD76I/O Parallel Port Automatic Feed XT. When this signal is low, the printer automatically line feed after printing each line. This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 KW resistor.AEN18I Address Enable. When this input is high, it disables function selection via A15-A0. Access during DMA transfer is not affected by this pin./ASTRB79O EPP Address Strobe. This signal is used in EPP mode as address strobe. It is an active low signal.BADDR0, BADDR172, 71I Base Address. These bits determine one of the four base addresses from which the Index and Data Registers are offset. An internal pull- down resistor of 30 KW is on this pin. Use a 10 KW resistor to pull this pin to VCC.BOUT1, BOUT271, 63O UARTs Baud Output. This multi-function pin supports the associated serial channel Baud Rate generator output signal if the test mode is selected in the Power and Test Configuration Register and the DLAB bit (LCR7) is set. After the Master Reset, this pin offers the SOUT function.BUSY82I Parallel Port Busy. This pin is set high by the printer when it cannot accept another character. It has a nominal 25 KW pull-down resistor attached to it.CFG063I SIO Configuration Strap. These CMOS inputs select 1 of 4 default configurations in which the PC87338 powers up. An internal pull-down resistor of 30 KW is on this. Use a 10 KW resistor to pull these pins to VCC. CFG0 is multiplexed with SOUT2, BOUT2 and IRTX./CS0, /CS151, 3O Programmable Chip Select. /CS0, 1 are programmable chip select and/or latch enable and/or output enable signals that can be used as game port, I/O expand, etc. The decoded address and the assertion conditions are configured via the 87338VJG’s configuration registers.