Acer Extensa 610 Service Guide

2-24Service Guide2.4ALI M7101 (Power Management Unit)
2.4.1Features
· Four operating states - ON, DOZE, SLEEP, APM
· Programmable DOZE and SLEEP timer
· Programmable EL timer for backlight control
· Two Programmable APM timers
· Two output pins depending on operating state, each pin is programmable and power
configurable
· Provides system activity and EL activity monitorings, includes
· Video
· Harddisk
· Floppy
· Serial port
· Parallel port
· Keyboard
· Six programmable I/O address groups activity...

Major Chips Description2-252.4.2Pin Diagram                                                                          Vss
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CBEJ2
VDD5
FRAMEJ
IRDYJ
TRDYJ
DEVSELJ
PAR
CBEJ1
SMIJ
Vss
AD15
AD14
AD13
AD12
AD11
AD101
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA3
GPIOA2
GPIOA1
GPIOA0
Vss
CLK32
SEL1
SEL0
VDD5
DISPLAY
CCFT
FPVEE
SPKCTL
SQWO
SLED
DRQ
CRT75
74
73
72
71
70
69
68
67
66
65
64
63
62
61...

2-26Service Guide2.4.3Pin Description
Table 2-4M7101 Pin DescriptionsNameNo.TypeDescriptionPCI interface : (42)PCICLK89IPCI Clock.  This is the PCI Bus interface CLK input signal.  This
clock frequency should not be more than 33 Mhz.  It is used by
internal PCI interface.AD[31:0]91-98,2-
9, 20-
25, 27,
28, 30-
37I/OPCI Address and Data bus.  These lines are connected to PCI Bus’
AD[31:0].   These lines contain Address and Data bus information
for PCI transaction.CBEJ[3:0]99,10,
17,29IPCI Bus Command and...

Major Chips Description2-27Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU Input event interface : (11)LBJ47ILow Battery.  First stage battery low indication. If low is detected
and Low Battery Timer is timeout, then battery low 1 SMIJ will be
generated every programmed interval time until battery low 2 SMIJ
is asserted or LB timer is reset. No debounce circuit is built in. Only
low level is detected.LLBJ48ILow Low Battery.  Second stage battery low indication.  If low is
detected...

2-28Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU Input event interface : (11)PS250IExternal PS2 MOUSE.  This signal represents whether the PS2
MOUSE is plugged in or not.  When a PS2 MOUSE is plugged in, a
high to low transition will generate a SMIJ.  When a PS2 MOUSE is
pulled out, a low to high transition will generate a SMIJ as well.  In
addition, the signal status can be read from BEEPER offset 0CBh
D1 register.  Debounce circuit is built in.  It detects both...

Major Chips Description2-29Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPMU output interface (9)CCFT57OBacklight control.  This signal is used to turn on/off LCD backlight.
FPVEE will AND with offset 0D2h D0 to generate CCFT.  That is, if
both FPVEE and offset 0D2h D0 are high then CCFT will be high or
1Khz signal with programmed duty cycle by offset 0Fbh D[4:0].
Otherwise CCFT will be low.DISPLAY58OLCD Display On/Off control.  This signal is used to control the LCD
display ON/OFF....

2-30Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group AGPIOA6
/SPEKIN(70)ISpeak input.  When offset 0F6h D6=‘1’, this pin will be speaker
input. The input signal will xor with SPKCTL internally.GPIOA5
/GPIOWB(69)OExternal General Purpose I/O B write.  When SQWO is pull low
4.7K, the GPIOA5 will become GPIOWA.  External General purpose
A R/W control pulse,  When write index 0F0h with a byte or a word.
A 74373 latch...

Major Chips Description2-31Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group AGPIOA0
/GPIORAJ(64)OExternal General Purpose I/O A read.  When SPKCTL is pull low
4.7K, the GPIOA0 will become GPIORAJ.  External General
purpose A Read control pulse,  When Read index 0E1h with a byte
or a word.  A 74245 OEJ pulse will be generated at this pin.  The
74245 output should be connected to PCI AD[23:16] if a byte
command.  If a word command,...

2-32Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group BGPIOB3
/IN_BRDYJ(84)IBRDYJ Input.  When DISPLAY is pulled low, this pin will be BRDYJ
input. It must be connected to CPU.GPIOB2
/IN_INIT(83)IINIT Input.  When DISPLAY is pulled low, this pin will be INIT input.GPIOB1
/IN_SMIJ(82)ISMIJ Input.  When DISPLAY is pulled low, this pin will be SMIJ
input.GPIOB0
/IN_INTR(81)ISMIJ Input.  When DISPLAY is pulled low, this...

Major Chips Description2-33Table 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionGeneral purpose I/O interface(24)General purpose I/O group CGPIOC5
/EXTSW(78)External suspend/resume switch.  When offset 0F6h D10=0, this
signal is  GPIOC5. When D10=1, this signal will become EXTSW.
External Suspend/Resume switch input. Pressing this switch will
generate SMIJ to suspend or resume the system. When the system
is at resume status(On, Doze), pressing this switch will enter
Suspend status(Sleep)....