Acer Extensa 610 Service Guide

2-14Service Guide2.3ALI M1523
The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in
the DMA controller.  This chip contains the keyboard controller, real-time clock and IDE master
controller.  This chip also supports the Advanced Programmable Interrupt controller (APIC)
interface.
One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes....

Major Chips Description2-15· 32-bit addressability
· Provides compatible DMA transfers
· Provides type F transfers
· Interrupt controller
· Provides 14 interrupt channels
· Independently programmable level/edge triggered channels
· Counter/Timers
· Provides 8254 compatible timers for system timer, refresh request, speaker output use
· Keyboard controller
· Built-in PS2/AT keyboard controller
· The specific I/O is used to save the external TTL buffer
· Real time clock
· Built-in real-time clock
· 128-byte...

2-16Service Guide2.3.2Block Diagram
M1523 Block DiagramDATA
Buffer
ControlAddress
BufferDecoderClock & ResetPCI BUS
Interface
UNITPCI
Arbiter
InterfaceISA
Interrupt
UNITPCI
Interrupt
UNITCPU
InterfaceUSB
Interface
(reserved)PCI
IDE
Master
InterfaceISA BUS
Interface
UNITDMA
Refresh
UNITPMU or APIC
InterfacePS2/AT
Keyboard
ControllerTimer
UNITMISC.
LogicREAL
Time
ClockPWG
CPURST
RSTDRV
OSC14MPCICLK
CBEJ[3:0]
AD[31:0]
FRAMEJ
TRDYJ
IRDYJ
STOPJ
DEVSELJ
SERRJ
PARPHOLDJ
PHLDAJFERRJ
IRQ[15:14]
IRQ[11:3]...

Major Chips Description2-172.3.3Pin Diagram                                                       VDD
IRQ12
MSCLK
KBDATA
KBCLK/KBCSJ
KBINH/IRQ1
IDESCS3J
IDESCS1J
IDEPCS3J
IDEPCS1J
IDE_A0
IDE_A2
IDE_A1
IDAKJ1
IDAKJ0
IDERDY
IDEIORJ
IDEIOWJ
IDRQ1
IDRQ0
IDE_D0
IDE_D15
Vss
IDE_D1
IDE_D14
IDE_D2
IDE_D13
IDE_D3
IDE_D12
IDE_D4
IDE_D11
IDE_D5
IDE_D10
IDE_D6
IDE_D9
IDE_D7
VDD
IDE_D8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CBEJ0
AD8
AD9
AD10
AD11
VDD Vss
BALE
SA2
SA1
SA0
SBHEJ
M16J
LA23
IO16J
LA22
IRQ10
LA21
IRQ11
VDD/BAT...

2-18Service Guide2.3.4Signal Descriptions
Table 2-3M1523 Signal DescriptionsSignalPinTypeDescriptionClock and ResetPWG17IPower-Good Input.  This signal comes from the power
supply to indicate that power is available and stable.CPURST49OCPU Reset includes cold and warm reset 3.3V signal
(connected to CPU INIT)RSTDRV57OCPU Cold Reset.  3.3V signal (connected to CPU RESET)OSC14M43I14.318Mhz Clock Input.  This is used for 8254 timer clock.PCI InterfacePCICLK71IPCI clock for internal PCI...

Major Chips Description2-19Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionPCI Interrupt UnitINTAJ_MI67IPCI Interrupt Input A or PCI interrupt polling input.INTBJ68I/OPCI Interrupt Input B or polling select_0 output.INTCJ69I/OPCI Interrupt Input C or polling select_1 output.INTDJ70I/OPCI Interrupt Input D or polling select_2 output.PCI ArbiterPHOLDJ66OM1523 requests the ownership of the PCI bus.
  Hardware setting option
  Pull low : internal RTC is enabled
  Pull high : external...

2-20Service GuideTable 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionISA InterfaceSA[16:0]181, 185, 187,
188, 190, 192,
193, 195, 197,
199, 201, 203,
205, 207, 3, 4,
5I/OISA Slot Address Bus.  These lines are addresses
connected to slot address.SBHEJ6I/OISA Slot Byte-high Enable.  In a CPU or PCI master cycle,
this signal is generated by BE3J-BE0J and the chip’s
internal control circuit.  In a DMA cycle, it is generated by
internal 8237.  In a refresh cycle, it is generated by the...

Major Chips Description2-21Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionISA InterfaceSMEMRJ / LMEGJ176OISA System Memory Read.  When the internal RTC is
enabled, this signal indicates that the memory read cycle
is for an address below 1-MB address.  Otherwise, this pin
only indicates an address below 1M byte.SMEMWJ / RTCAS174OISA System Memory Write.  When the internal RTC is
enabled, this signal indicates that the memory write cycle
is for an address below 1-MB address....

2-22Service GuideTable 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionMiscellaneousMSCLK154OMouse Clock Output when the internal KBC is enabled.RTC32KI16IRTC 32.768K Osc1.  This is crystal input and requires an
external 32.768khz quartz crystal.RTC32KII15IRTC 32.768K Osc2.  This is crystal input and requires an
external 32.768khz quartz crystal.SIRQI44ISteerable IRQ Input 1SIRQII/IRQ8J45ISteerable IRQ Input 2 when the internal RTC is enabled.
RTC interrupt input when the internal RTC is...

Major Chips Description2-23Table 2-3M1523 Signal Descriptions (continued)SignalPinTypeDescriptionIDE InterfaceIDE_D[15:0]135, 132, 130,
128, 126, 124,
122, 119, 121,
123, 125, 127,
129, 131, 133,
136I/OIDE ATA Data BusVcc and VssVCC353PVcc 3.3VVCC5/VBAT14PRTC Battery InputVCC540, 72, 105,
120, 156, 208PVCC 5.0V(VDD)Vss1, 26, 52, 82,
104, 134, 157,
182PVss or Ground.