Acer Extensa 610 Service Guide

2-4Service Guide2.2.2Block Diagram586
CPUSRAMM1521
BGADRAMHDDM1523UMA
Graphic
controllerIDE Master
Aladdin III System Block DiagramCDCPU BusPCI BusISA BusUSB connectorFigure 2-1Alladin III Block Diagram 

Major Chips Description2-52.2.3System ArchitectureM1521M1523ALADDIN-III SYSTEM ARCHITECTUREtag 8/11-bitTTLSRAM
208-PQFP/RTC/KBC328-BGA586 CPU
addrdataPCIISADRAM MDGCMA
CTLRIDE bus
HDD128K/256K
FlashXD - TTLUSB connFigure 2-2Alladin III System Architecture 

2-6Service Guide2.2.4Data PathE C C64-bitSWAPHD_
OUT64-bitSWAP6 DWORD5 DWORD6 DWORDMUXPCI_OUTPCI_INP_IN[31:0]PB_OUT[63:0]64-bitHDIN[63:0]MUX72-bitECC72-bitSWAP8 QWORDMUXMUXMUXMDIN[63:0]PCI_INMD_IN[63:0]PB_IN[63:0]HD_INSWAPH/L DW swapfor 32-bit DRAMMD_OUTM1521MD_INECC partial
W-R pathFigure 2-3M1521 Data Path 

Major Chips Description2-72.2.5Pin DiagramFigure 2-4M1521 Pin Diagram 

2-8Service Guide2.2.6Signal Descriptions
Table 2-2M1521 Signal DescriptionsSignalPinTypeDescriptionHost InterfaceA[31:29]
A[28:26]
A[25:23]
A[22:20]
A[19:17]
A[16:14]
A[13:11]
A[10:08]
A[07:05]
A[04:03]W8, W11, U11, Y10,
Y9, V10, W9, W10, U9,
U10, V9, U5, V5, W5,
Y5, U6, W6, V6, Y6,
U7, W7, Y7, V7, V8,
Y8, Y12, U8, Y11, V11I/OHost Address Bus Lines.  A[31:3] have two
functions.  As inputs, along with the byte enable
signals, these serve as the address lines of the host
address bus that defines the...

Major Chips Description2-9Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionHost InterfaceM/IOJH5IHost Memory or I/O.  This bus definition pin
indicates the current bus cycle is either memory or
input/ output.D/CJT7IHost Data or Code.  This bus definition pin is used to
distinguish data access cycles from code access
cycles.W/RJT9IHost Write or Read.  When WRJ is driven high, it
indicates the current cycle is a write.  Inversely, if
WRJ is driven low, a read cycle is...

2-10Service GuideTable 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionDRAM InterfaceRASJ[6] /
SCASJ[0]M16ORow Address Strobe 6, or Synchronous DRAM CAS
0 (FPM/EDO/BEDO) of DRAM bank 6. SDRAM
column address strobe (SDRAM) copy 0.RASJ[5:0] /
SCSJ[5:0]N17, M17, E16, F16,
F17, G17I/ORow Address Strobes or synchronous DRAM chip
select.  These signals drives the corresponding
RASJs of DRAMs or synchronous DRAM chip
select[5:0].CASJ[7:0] /
DQM[7:0]L16, G16, J16, H16,
L17, H17, K17, J17OColumn...

Major Chips Description2-11Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionSecondary Cache InterfaceCCSJ/CB4W16OSynchronous SRAM chip select or Cache Address
line 4 copy.  This pin has two modes of operation
depending on the type of SRAM selected via
hardware strapping options or programming the CC
register.GWEJY16OSynchronous SRAM Global Write Enable or
Asynchronous SRAM Write Enable.COEJU15OSynchronous/Asynchronous SRAM Output Enable.BWEJ/CGCSJY17OSynchronous SRAM Byte-Write...

2-12Service GuideTable 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionTRDYJE8I/OTarget Ready.  This indicates the target is ready to
complete the current data phase of transaction.STOPJE11I/OStop.  This indicates the target is requesting the
master to stop the current transaction.LOCKJE5I/OLock Resource Signal.  This indicates the PCI
master or the bridge intends to do exclusive
transfers.REQJ[3:0]D13, D11, D9, D7IBus request signals of PCI Masters.  When asserted,
it means the PCI...

Major Chips Description2-13Table 2-2M1521 Signal Descriptions (continued)SignalPinTypeDescriptionUMA InterfaceMGNTJ/
GNTJ[4]F7OMemory Grant.  This output connects to the MGNTJ
of the GUI device.   This pin can also be used as
grant signal of the fifth PCI master.PRIOG15IPriority.  The high priority request from the GUI
device.Power PinsVCCF5, F6, G6, R6, R7,
F14, F15, P15, R15,
R16PVcc 3.3VVDD_5E14PVcc 5.0VVss or GndE15, T16, J9, J10, J11,
J12, K9, K10, K11,
K12, L9, L10, L11, L12,
M9, M10, M11, M12PGround