Acer Extensa 610 Service Guide

2-44Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface (continued)43BE0# (BLE#)InByte Enable 0. Indicates data transfer on D7:D0 for the
current cycle.32BE1#InByte Enable 1. Indicates data transfer on D15:D8 for the
current cycle.21BE2#InByte Enable 2. Indicates data transfer on D23:D16 for the
current cycle.10BE3#InByte Enable 3. BE3# indicates that data will transfer over the
data bus on D31 :24 during the current access.179
180
182...

Major Chips Description2-45Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface (continued)51
50
49
48
47
46
45
44
41
40
38
37
36
35
34
33
20
19
18
17
16
15
14
13
8
7
6
5
4
3
2
1D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OSystem Data Bus.  In...

2-46Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)31PARI/OParity.  This signal is used to maintain even parity across
AD0-31 and C/BE0-3#.  PAR is stable and valid one clock
after the address phase.  For data phases, PAR is stable and
valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one clock after the
completion of the current...

Major Chips Description2-47Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)30SERR# (MCLKOUT)ODSystem Error.  Used to report system errors where the result
will be catastrophic (address parity error, data parity errors
for Special Cycle commands, etc.).  This output is actively
driven for a single PCI clock cycle synchronous to CLK and
meets the same setup and hold time requirements as all
other bused signals.  SERR# is not driven high by the chip...

2-48Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)51
50
49
48
47
46
45
44
41
40
38
37
36
35
34
33
20
19
18
17
16
15
14
13
8
7
6
5
4
3
2
1AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OPCI Address /...

Major Chips Description2-49Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)43
32
21
10C/BE0#
C/BE1#
C/BE2#
C/BE3#In
In
In
InBus Command / Byte Enables. During the address phase. of
a bus transaction, these pins define the bus command see
list below:
C/BE3-0              Command Type                        655500000Interrupt Acknowledge
0001Special Cycle
0010I/O ReadY
0011I/O WriteY
0100-reserved-
0101-reserved-
0110Memory ReadY
0111Memory WriteY...

2-50Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionPCI Bus Interface (continued)90
91
92
93
94
95
96
97
98CA0 (P16)
CA1 (P17)
CA2 (P18)
CA3 (P19)
CA4 (P10)
CA5 (P21)
CA6 (P22)
CA7 (P23)
CA8 (BLANK)Out
Out
Out
Out
Out
Out
Out
Out
I/OAddress bus for DRAM C.
CA0-7 may be configured as flat panel data output (P16-23).
See also pins 71-88 (in Flat Panel Display interface pin
descriptions section).
CA8 may be configured as VAFC BLANK# out or vertical
reference input...

Major Chips Description2-51Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionDisplay Memory Interface162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177MAD0
MAD1
MAD2 (CFG10)
MAD3 (CFG11)
MAD4 (CFG12)
MAD5 (CFG13)
MAD6 (CFG14)
MAD7 (CFG15)
MAD8 (PCI ROMD0)
MAD9 (PCI ROMD1)
MAD10 (PCI ROMD2)
MAD11 (PCI ROMD3)
MAD12 (PCI ROMD4)
MAD13 (PCI ROMD5)
MAD14 (PCI ROMD6)
MAD15 (PCI ROMD7)I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OMemory data bus for DRAM A....

2-52Service GuideTable 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionFlat Panel Display Interface71
72
73
74
75
76
78
79
81
82
83
84
85
86
87
88P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit
panel interfaces may also be supported (see CA0-7 for P16-
23).
Refer to Table 2-7 for the configurations for various panel
types.70SHFCLKOutShift Clock.  Pixel...

Major Chips Description2-53Table 2-10C&T 65550 Pin Descriptions (continued)Pin#Pin NameTypeDescriptionFlat Panel Display Interface (continued)55RSETInSet point resistor for the internal color palette DAC.  A 560 W
1% resistor is required between RSET and AGND.59
56AVCC
AGNDVCC
GNDAnalog power and ground pins for noise isolation for the
internal color palette DAC.  AVCC should be isolated from
digital VCC as described in the Functional Description of the
internal color palette DAC.  For proper DAC...