Acer Extensa 610 Service Guide

2-74Service GuideTable 2-13PCI1131 Pin Descriptions (Continued)     TERMINALNAME         NOI /OTYPEFUNCTIONInterrupt TerminalsIRQ15/
RI_OUT            163I/OInterrupt Request 15. This terminal indicates an interrupt request
from one of the PC Cards. RI_OUT allows the RI input from the 1 6-
bit PC Card, CSTSCHG from CardBus Cards or PC Card removal
events to be output to the system. This signal is configured in the
Card Control Register of the TI Extension Registers.PC Card Power Switch TerminalsLATCH...

Major Chips Description2-752.7NS87336VJG Super I/O Controller
The PC87336VJG is a single chip solution for most commonly used I/O peripherals in ISA, and
EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs,
and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the
peripherals and a set of configuration registers are also implemented in this highly integrated
member of the Super l/O family. Advanced power management features, mixed...

2-76Service Guide· The Bidirectional Parallel Port:
· Enhanced Parallel Port(EPP) compatible
· Extended Capabilities Port(ECP) compatible, including level 2 support
· Bidirectional under either software or hardware control
· Compatible with ISA, and EISA, architectures
· Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy
Disk Drive(FDD)
· Includes protection circuit to prevent damage to the parallel port when a connected
printer is powered up or is operated at a...

Major Chips Description2-77· Plug and Play Compatible:
· 16 bit addressing(full programmable)
· 10 selectable IRQs
· 3 selectable DMA Channels
· 3 SIRQ Inputs allows external devices to mapping IRQs
· 100-Pin TQFP package - PC87336VJG
2.7.2Block DiagramConfiguration
RegistersUART
(16550 or 16450)UART
+ IrDA/HP & Sharp IR
(16550 or 16450)General
Purpose
RegistersPower
Down LogicIEEEE1284
Parallel PortHifh Current DriverFloppy Disk
Controller with
Digital Data
Separator
(Enhabced 8477)I/O PortsControl...

2-78Service Guide2.7.3Pin DiagramFigure 2-16NS87336VJG Pin Diagram 

Major Chips Description2-792.7.4Pin Description
Table 2-14NS87336VJG Pin DescriptionsPinNo.I/ODescriptionA15-A067, 64,
62-60,
29, 19-
28IAddress.  These address lines from the microprocessor determine which
internal register is accessed.  A0-A15 are dont cares during DMA
transfer./ACK83IParallel Port Acknowledge.  This input is pulsed low by the printer to
indicate that it has received the data from the parallel port.  This pin has
a nominal 25 KW pull-up resistor attached to it.ADRATE0,
ADRATE196,...

2-80Service GuideTable 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescription/CS0,
/CS151, 3OProgrammable Chip Select.  /CS0, 1 are programmable chip select
and/or latch enable and/or output enable signals that can be used as
game port, I/O expand, etc.  The decoded address and the assertion
conditions are configured via the 87336VJG’s configuration registers./CTS1,
/CTS272, 64IUARTs Clear to Send.  When low, this indicates that the modem or
data set is ready to exchange data.  The /CTS signal...

Major Chips Description2-81Table 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescriptionDENSEL
(Normal Mode)46OFDC Density Select.  DENSEL indicates that a high FDC density data
rate (500 Kbs, 1 Mbs or 2 Mbs) or a low density data rate (250 or 300
Kbs) is selected.  DENSEL is active high for high density (5.25-inch
drives) when IDENT is high, and active low for high density (3.5-inch
drives) when IDENT is low.  DENSEL is also programmable via the
Mode command.DENSEL
(PPM Mode)76OFDC Density...

2-82Service GuideTable 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescription/DRV247IFDD Drive2.  This input indicates whether a second disk drive has
been installed.  The state of this pin is available from Status Register
A in PS/2 mode.  (See PNF for further information)./DSKCHG
(Normal Mode)30IDisk Change.  The input indicates if the drive door has been opened.
The state of this pin is available from the Digital Input Register.  This
pin can also be configured as the RGATE data separator...

Major Chips Description2-83Table 2-14NS87336VJG Pin Descriptions (continued)PinNo.I/ODescriptionIORCHDY51OI/O Channel Ready.  When IORCHDY is driven low, the EPP extends
the host cycle.IRQ3, 4
IRQ5-7
IRQ9-11
IRQ12, 15
(PnP Mode)99, 98
96-94,
55-57,
66, 58I/OInterrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15.  This pin can be a totem-
pole output or an open-drain output.  The interrupt can be sourced by
one of the following: UART1 and/or UART2, parallel port, FDC,
SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.
IRQ5 is...