Acer Extensa 610 Service Guide

2-34Service GuideTable 2-4M7101 Pin Descriptions (Continued)NameNo.TypeDescriptionPower PinsVDD5 x 311,59,76P5V VDD inputVDD3 x 226,100P3.3V VDD inputVDDS x 146P5V Suspend VDD input.   This pin supplies to RI, RTC, HOTKEYJ,
COVSW, SUSTATE, PWGD, SUSRSTJ pad.VSS x 51,19,38,
63,90PVSS Ground.2.4.4Different Pin definition setting
· SLED, CCFT, DISPLAY, SPKCTL, SQWO and GPIOC2 pins are all internal pull high 50K
ohms.  The blank part of following table means keeping the original pin definition.
· When SLED...

Major Chips Description2-35When offset 0F6h, D5=1 and offset 0FBh, D7=1; GPIOB[7:0] and GPIOA[7:0] output some clocks
for testing.  The clocks are OTCOUNT, O16K, TCLK2, TCLK3, O128HZ, O16HZ, O8HZ, O4HZ,
O2HZ, O1Hz, ELCOUNT, DZCOUNT, SLCOUNT, RICOUNT, LBCOUNT[1:0].
Table 2-6M7101 Original Pin Definition...

2-36Service Guide2.4.5Numerical Pin List
Table 2-7M7101 Numerical Pin ListNo.Pin NameTypeNo.Pin...

Major Chips Description2-372.4.6Alphabetical Pin List
Table 2-8M7101 Alphabetical Pin ListNo.Pin NameTypeNo.Pin...

2-38Service Guide2.4.7Function Description
The function blocks of M7101 are as follows :
1. PCI Interface
2. State Controller
3. Timer
4. Wake up event handler
5. Activity monitor
6. Battery monitor
7. General Purpose Input/Output (GPIO)
8. SMIJ Generator
9. SUSPEND monitor
10. APM monitor
11. Rundown Emulation
12. LCD control
13. SLOWDOWN control
PCI interface
The PCI interface is running at PCICLK frequency.  From the point of PCI bus, M7101 is a hidden
component.  There are no PCI configuration spaces...

Major Chips Description2-39Table 2-9M7101 PCI Interface Lock RegisterActionI/O Port0178h/0078hI/O Port 017Ah/007AhLock Readnot available
except offset
0D1hnot available except offset 0D1hLock Writenot available
except offset
0D1hnot available except offset 0D1hUnlock
ReadavailableavailableUnlock
WriteavailableavailableState Machine for PCI Interface.
FRAMEJ=1IDLEnocycle=1, when FRAMEJ=1 and IRDYJ=1.
             =0, when others.HIT=1, when read/write port 178-17B.
=0, when others.FRAMEJ=1
FRAMEJ=0...

2-40Service Guide2.5   C&T 65550 High Performance Flat Panel/CRT VGA Controller
The C&T65550 of high performance multimedia flat panel / CRT GUI accelerators extend CHIPS’
offering of high performance flat panel controllers for full-featured note books and sub-notebooks.
The C&T65550 offers 64-bit high performance and new hardware multimedia support features.
2.5.1Features
HIGH PERFORMANCEBased on a totally new internal architecture, the C&T65550, integrates a powerful 64-bit graphics
accelerator engine...

Major Chips Description2-41The C&T65550 offers a variety of programmable features to optimize display quality. Vertical
centering and stretching are provided for handling modes with less than 480 lines on 480-line
panels. Horizontal and vertical stretching capabilities are also available for both text and graphics
modes for optimal display of VGA text and graphics modes on 800x600 and 1024x768 panels.
Three selectable color-to-gray scale reduction techniques and SMARTMAP™ are available for
improving the...

2-42Service Guide2.5.3Pin DiagramFigure 2-10C&T 65550 Pin Diagram 

Major Chips Description2-432.5.4Pin Descriptions
Table 2-10C&T 65550 Pin DescriptionsPin#Pin NameTypeDescriptionCPU Direct / VL-Bus Interface207RESETInReset.  For VL-Bus interfaces, connect to RESET#.  For
direct CPU local bus interfaces, connect to the system reset
generated by the mother board system logic for all
peripherals (not the RESET# pin of the processor).  This
input is ignored during Standby mode (STNDIBY# pin low) so
that the remainder of the system (and the system bus) may
be safely powered...