Acer Extensa 390 Service Guide

							Major Chips Description2-25 Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionKENJ/INVO
Group ACache Enable Output.  This signal is connected to the CPUs KENJ and INV
pins.  KENJ is used to notify the CPU whether the address of the current
transaction is cacheable.  INV is used during L1 snoop cycles.  The M1531
drives this signal high (low) during the EADSJ assertion of a PCI master write
(read) snoop cycle.SMIACTJI
Group ASMM Interrupt Active.  This signal is asserted by the CPU to inform the M1531
that SMM mode is being entered.HD[63:0]I/O
Group AHost Data Bus Lines.  These signals are connected to the CPUs data bus.
HD[63] applies to the most significant bit and HD[0] applies to the least
significant bit.MPD[7:0]I/O
Group CDRAM Parity /ECC check bits.  These are the 8 bits for parities/ECC check
bits over DRAM data bus.  MPD[7] applies to the most significant bit and
MPD[0] applies to the least significant bit.RASJ[7] /
SRASJ[0]O
Group CRow Address Strobe 7, (FPM/EDO) of DRAM row 7.
SDRAM Row Address Strobe (SDRAM) copy 0. It connects to SDRAM RASJ.
This is a multifunction pin and determined by Index-5Ch bit0.RASJ[6] /
SCASJ[0]O
Group CRow Address Strobe 6, (FPM/EDO) of DRAM row 6.
SDRAM Column address strobe (SDRAM) copy 0.  It connects to SDRAM
CASJ. This is a multifunction pin and determined by Index-5Ch bit0.RASJ[5:0]O
Group CRow Address Strobes.  These signals are used to drive the corresponding
RASJs of FPM/EDO DRAMs.  In SDRAM, they are used to drive the
corresponding SDRAM CSJs.CASJ[7:0] /
DQM[7:0]O
Group CColumn Address Strobes or Synchronous DRAM Input/Output Data Mask.
These CAS signals should be connected to the corresponding CASJs of each
bank of DRAM.  The value of CASJs equals that of HBEJs for write cycles.
During DRAM read cycles, all of CASJs will be active.  In SDRAM, these pins
act as synchronized output enables during a read cycle and the byte mask
during write cycle, these pins are connected to SDRAM DQM[7:0].MA[11:2]O
Group CDRAM Address Lines.  These signals are the address lines[11:2] of all
DRAMs.  The M1531 supports DRAM types ranging from 256K to 64Mbits.MAA[1:0]O
Group CMemory Address copy A for [1:0].  These signals are the address lines[1:0]
copy 0 of all DRAMs.MAB[1:0]O
Group CMemory Address copy B for [1:0].  These signals are the address lines[1:0]
copy 1 of all DRAMs.MWEJ[0]O
Group CDRAM Write Enable.  This is the DRAM write enable pin and behaves
according to the early-write mechanism, i.e. , it activates before the CASJs do.
For refresh cycles, it will remain deasserted.MD[63:0]I/O
Group CMemory Data.  These pins are connected to DRAM’s data bits.  MD[63]
applies to the most significant bit and MD[0] applies to the least significant bit.CLKEN[0]/
REQJ[4]I/O
Group CSDRAM Clock Enable Copy 0 or PCI Master Request.  This signal is used as
SDRAM clock enable copy 0 to do self refresh during suspend.  It can also be
used as bus request signal of the fifth PCI master.  This function is controlled
by Index -5Dh bit 1. 
						

							2-26Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionCLKEN[1]/
GNTJ[4]O
Group CSDRAM Clock Enable Copy 1 or PCI Master Grant.  This signal is used as
SDRAM clock enable copy 1 to do self refresh during suspend.   It can also be
used as grant signal of the fifth PCI master.  This function is controlled by
Index -5Dh bit 1.Secondary Cache Interface   3.3V/2.5V  ToleranceCADVJO
Group ASynchronous SRAM Advance.  This signal will make PBSRAM/Memory Cache
internal burst address counter advance.CADSJO
Group ASynchronous SRAM Address Strobe.  This signal connects to PBSRAM/
Memory Cache ADSCJ.CCSJO
Group ASynchronous SRAM Chip Select.  This signal connects to PBSRAM/Memory
Cache CE1J to mask ADSPJ and enable ADSCJ sampling.GWEJO
Group ASynchronous SRAM Global Write Enable.  This signal will write all the byte
lanes data into PBSRAM/Memory Cache.COEJO
Group ASynchronous SRAM Output Enable.  This signal will enable the data output
driving of PBSRAM/Memory Cache.BWEJO
Group ASynchronous SRAM Byte-Write Enable.  This signal connects to byte write
enable of PBSRAM/Memory Cache.TIO[10]/
MWEJ[1]/
MKREFRQJI/O
Group CSRAM Tag[10] or another copy of MWEJ or DRAM Cache MKREFRQJ.  This
pin is used for multifunction.  It can be SRAM tag address bit 10, or another
copy of MWEJ connected to DRAM, or MKREFRQJ connected to DRAM
Cache.  Refer to Register Index-41h bit 6, bit3 and bit0 description.TIO[9]/
SRASJ[1]I/O
Group CSRAM Tag[9] or Synchronous DRAM (SDRAM) RAS copy 1.  This pin is used
for multifunction.  It can be SRAM tag address bit 9, or another copy of
SRASJ connected to SDRAM.  Refer to Register Index-41h bit3 and bit0
description.TIO[8]/
SCASJ[1]I/O
Group CSRAM Tag[8] or Synchronous DRAM (SDRAM) CAS copy 1.  This pin is used
for multifunction.  It can be SRAM tag address bit 8, or another copy of
SCASJ connected to SDRAM.  Refer to Register Index-41h bit3 and bit0
description.TIO[7:0]I/O
Group BSRAM Tag[7:0].  This pin contains the L2 tag address for 256-KB L2 caches.
TIO[6:0] contain the L2 tag address and TIO7 contains the L2 cache valid bit
for 512-KB caches.  TIO[5:0] contain L2 tag address, TIO7 contains L2 cache
valid bit and TIO6 contains the L2 cache dirty bit for 1-MB cache.  Refer to
index-41h cache configuration table.TAGWEJO
Group BTag Write Enable.  This signal, when asserted, will write into the external tag
new state and tag addresses.PCI Interface   3.3V/2.5V   ToleranceAD[31:0]I/O
Group BPCI Address and Data Bus Lines.  These lines are connected to the PCI bus.
AD[31:0] contain the information of address or data for PCI transactions.CBEJ[3:0]I/O
Group BPCI Bus Command and Byte Enables.  Bus commands and byte enables are
multiplexed in these lines for address and data phases, respectively.FRAMEJI/O
Group BCycle Frame of PCI Buses.  This indicates the beginning and duration of a
PCI access. It will be as an output driven by M1531 on behalf of CPU, or as
an input during PCI master access. 
						

							Major Chips Description2-27 Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionDEVSELJI/O
Group BDevice Select.  When the target device has decoded the address as its own
cycle, it will assert DEVSELJ.IRDYJI/O
Group BInitiator Ready.  This signal indicates the initiator is ready to complete the
current data phase of transaction.TRDYJI/O
Group BTarget Ready.  This pin indicates the target is ready to complete the current
data phase of transaction.STOPJI/O
Group BStop.  This signal indicates the target is requesting the master to stop the
current transaction.LOCKJI/O
Group BLock Resource Signal.  This pin indicates the PCI master or the bridge intends
to do exclusive transfers.REQJ[3:0]I
Group BBus Request signals of PCI Masters.  When asserted, it means the PCI
Master is requesting the PCI bus ownership from the arbiter.GNTJ[3:0]O
Group BGrant signals to PCI Masters.  When asserted by the arbiter, it means the PCI
master has been legally granted to own the PCI bus.PHLDJI
Group BPCI bus Hold Request.  This active low signal is a request from M1533/M1543
for the PCI bus.PHLDAJO
Group BPCI bus Hold Acknowledge.  This active low signal grants PCI bus to
M1533/M1543.PARI/O
Group BParity bit of PCI bus.  It is the even parity bit across PAD[31:0] and CBEJ[3:0].SERRJ/
CLKRUNJI/O
Group BSystem Error or PCI Clock RUN.  If the M1531 detects parity errors in
DRAMs, it will assert SERRJ to notify the system.  As CLKRUNJ, this signal
will connect to M1533 CLKRUNJ to start, or maintain the PCI CLOCK.  It is a
multifunction pin and determined by Index-77h bit0.Clock, Reset, and SuspendHCLKINI
Group ACPU bus Clock Input.  This signal is used by all of the M1531 logic that is in
the Host clock domain.RSTJI
Group BSystem Reset.  This pin, when asserted, resets the M1531 state machine, and
sets the register bits to their default values.Clock, Reset, and SuspendPCICLKI
Group BPCI bus Clock Input.  This signal is used by all of the M1531 logic that is in
the PCI clock domain.PCIMRQJO
Group BTotal PCI Request.  This signal is used to notify M1533/M1543 that there is
PCI master requesting PCI bus.SUSPENDJI
Group CSuspend.  When actively sampled, the M1531 will enter the I/O suspend
mode.  This signal should be pulled high when the suspend feature is
disabled.OSC32KOI
Group CThe refresh reference clock of frequency 32 KHz during suspend mode.  This
signal should be pulled to a fixed value when the suspend feature is disabled. 
						

							2-28Service GuideTable 2-3M1531 Signal DescriptionsSignalTypeDescriptionPower PinsVCC_APVcc 3.3V or 2.5V Power for Group A.  This power is used for CPU interface
and L2 control signals.  If this power connects to 3.3V, the relative signals will
output 3.3V and accept 3.3V input.  If this power connects to 2.5V, the relative
signals will output 2.5V and accept 2.5V input.VCC_BPVcc 3.3V Power for Group B.  This power is used for PCI interface and Tag
signals.  It must connect to 3.3V.  The relative signals will output 3.3V and 5V
input tolerance.VCC_CPVcc 3.3V Power for Group C.  This power is used for DRAM interface signals
during normal operation and suspend refresh.  It must connect to 3.3V.  The
relative signals will output 3.3V and 5V input tolerance.VDD_5PVcc 5.0V Power for Group A and Group B.  This pin supplies the 5V input
tolerance circuit and the core power for the internal circuit except the suspend
circuit.VDD_5SPVcc 5.0V Power for Group C.  This pin supplies the 5V input tolerance circuit
and the core power for the internal suspend circuit.Vss or GndPGround2.2.1.4 Numerical Pin List
Table 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeA1---C11CBEJ3I/OF1BRDYJOA2PHLDAJOC12AD28I/OF2BOFFJOA3AD3I/OC13REQJ1IF3SMIACTJIA4AD6I/OC14GNTJ0OF4HLOCKJIA5AD8I/OC15MPD4I/OF5ADSJIA6AD12I/OC16MD30I/OF6VCC_BPA7PARI/OC17MD25I/OF14VCC_CPA8TRDYJI/OC18MD58I/OF15VCC_CPA9AD17I/OC19MD26I/OF16MD50I/OA10AD22I/OC20MD59I/OF17MD18I/OA11AD25I/OD1BEJ6IF18MD51I/OA12AD30I/OD2BEJ5IF19MD19I/OA13REQJ3ID3BEJ4IF20MD52I/OA14GNTJ2OD4AD0I/OG1HD63I/OA15GNTJ3OD5AD1I/OG2CACHEJIA16MPD2I/OD6AD9I/OG3AHOLDOA17MPD0I/OD7AD14I/OG4KENJOA18MD61I/OD8LOCKJI/OG5NAJOA19MD29I/OD9FRAMEJI/OG6VCC_APA20MD62I/OD10AD19I/OG15VCC_CP 
						

							Major Chips Description2-29 Table 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeB1BEJ0ID11AD23I/OG16MD15I/OB2PHLDJID12AD27I/OG17MD48I/OB3AD2I/OD13REQJ0IG18MD16I/OB4AD5I/OD14MPD7I/OG19MD49I/OB5AD7I/OD15MPD3I/OG20MD17I/OB6AD11I/OD16MD55I/OH1HD60I/OB7CBEJ1I/OD17MD23I/OH2HD61I/OB8DEVSELJI/OD18MD56I/OH3HD62I/OB9AD16I/OD19MD24I/OH4WRJIB10AD21I/OD20MD57I/OH5MIOJIB11AD24I/OE1DCJIH8GNDPB12AD29I/OE2HITMJIH9GNDPB13REQJ2IE3EADSJOH10GNDPB14GNTJ1OE4BEJ7IH11GNDPB15MPD5I/OE5RSTJIH12GNDPB16MPD1I/OE6PCIMRQJOH13GNDPB17MD63I/OE7AD13I/OH16MD45I/OB18MD27I/OE8SERRJI/OH17MD13I/OB19MD60I/OE9IRDYJI/OH18MD46I/OB20MD28I/OE10AD18I/OH19MD14I/OC1BEJ3IE11PCLKINIH20MD47I/OC2BEJ2IE12AD26I/OJ1HD55I/OC3BEJ1IE13AD31I/OJ2HD56I/OC4AD4I/OE14MPD6I/OJ3HD57I/OC5CBEJ0I/OE15MD31I/OJ4HD58I/OC6AD10I/OE16MD20I/OJ5HD59I/OC7AD15I/OE17MD53I/OJ8GNDPC8STOPJI/OE18MD21I/OJ9GNDPC9CBEJ2I/OE19MD54I/OJ10GNDPC10AD20I/OE20MD22I/OJ11GNDPJ12GNDPM16MD35I/OT3HD23I/OJ13GNDPM17MD3I/OT4HD24I/OJ16MD10I/OM18MD36I/OT5HD25I/OJ17MD43I/OM19MD4I/OT6HD0I/OJ18MD11I/OM20MD37I/OT7A12I/OJ19MD44I/ON1HD36I/OT8A5I/OJ20MD12I/ON2HD37I/OT9GWEJOK1HD51I/ON3HD38I/OT10COEJOK2HD52I/ON4HD39I/OT11CADVJO 
						

							2-30Service GuideTable 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeK3HD53I/ON5HD40I/OT12TWEJOK4HD54I/ON8GNDPT13MAA0OK5HCLKININ9GNDPT14MAA1OK8GNDPN10GNDPT15TIO8I/OK9GNDPN11GNDPT16TIO9I/OK10GNDPN12GNDPT17TIO10I/OK11GNDPN13GNDPT18RASJ1OK12GNDPN15VDD5SPT19RASJ0OK13GNDPN16REQJ4I/OT20CASJ6OK16MD40I/ON17GNTJ4OU1HD16I/OK17MD8I/ON18MD1I/OU2HD17I/OK18MD41I/ON19MD34I/OU3HD18I/OK19MD9I/ON20MD2I/OU4HD19I/OK20MD42I/OP1HD31I/OU5HD20I/OL1HD46I/OP2HD32I/OU6HD1I/OL2HD47I/OP3HD33I/OU7A13I/OL3HD48I/OP4HD34I/OU8A8I/OL4HD49I/OP5HD35I/OU9CCSJOL5HD50I/OP6VCC_APU10BWEJOL8GNDPP15VCC_CPU11CADSJOL9GNDPP1632KIU12TIO0I/OL10GNDPP17SUSPENDJIU13TIO1I/OL11GNDPP18MD32I/OU14MAB0OL12GNDPP19MD0I/OU15MAB1OL13GNDPP20MD33I/OU16MA5OL16MD5I/OR1HD26I/OU17MWEJI/OL17MD38I/OR2HD27I/OU18RASJ4OL18MD6I/OR3HD28I/OU19RASJ3OL19MD39I/OR4HD29I/OU20RASJ2OL20MD7I/OR5HD30I/OV1HD15I/OM1HD41I/OR6VDD5PV2HD14I/OM2HD42I/OR7VCC_APV3HD13I/OM3HD43I/OR14VCC_BPV4HD6I/OM4HD44I/OR15VCC_CPV5HD3I/OM5HD45I/OR16RASJ6OV6A17I/OM8GNDPR17RASJ7OV7A14I/OM9GNDPR18CASJ2OV8A10I/OM10GNDPR19CASJ7OV9A4I/OM11GNDPR20CASJ3OV10A29I/O 
						

							Major Chips Description2-31 Table 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeM12GNDPT1HD21I/OV11A25I/OM13GNDPT2HD22I/OV12A24I/OV137A23I/OP1632KIC10AD20I/OV14TIO2I/OY10A3I/OB10AD21I/OV15MA2OV9A4I/OA10AD22I/OV16MA4OT8A5I/OD11AD23I/OV17MA8OY9A6I/OB11AD24I/OV18CASJ5OW9A7I/OA11AD25I/OV19CASJ1OU8A8I/OE12AD26I/OV20RASJ5OY8A9I/OD12AD27I/OW1HD12I/OV8A10I/OC12AD28I/OW2HD11I/OW8A11I/OB12AD29I/OW3HD10I/OT7A12I/OA12AD30I/OW4HD5I/OU7A13I/OE13AD31I/OW5HD2I/OV7A14I/OF5ADSJIW6A18I/OW7A15I/OG3AHOLDOW7A15I/OY7A16I/OB1BEJ0IW8A11I/OV6A17I/OC3BEJ1IW9A7I/OW6A18I/OC2BEJ2IW10A30I/OY6A19I/OC1BEJ3IW11A31I/OY5A20I/OD3BEJ4IW12A22I/OW13A21I/OD2BEJ5IW13A21I/OW12A22I/OD1BEJ6IW14TIO4I/OV137A23I/OE4BEJ7IW15TIO6I/OV12A24I/OF2BOFFJOW16MA3OV11A25I/OF1BRDYJOW17MA7OY12A26I/OU10BWEJOW18MA10OY13A27I/OG2CACHEJIW19CASJ0OY11A28I/OU11CADSJOW20CASJ4OV10A29I/OT11CADVJOY1HD9I/OW10A30I/OW19CASJ0OY2HD8I/OW11A31I/OV19CASJ1OY3HD7I/OD4AD0I/OR18CASJ2OY4HD4I/OD5AD1I/OR20CASJ3OY5A20I/OB3AD2I/OW20CASJ4OY6A19I/OA3AD3I/OV18CASJ5OY7A16I/OC4AD4I/OT20CASJ6OY8A9I/OB4AD5I/OR19CASJ7OY9A6I/OA4AD6I/OC5CBEJ0I/O 
						

							2-32Service GuideTable 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeY10A3I/OB5AD7I/OB7CBEJ1I/OY11A28I/OA5AD8I/OC9CBEJ2I/OY12A26I/OD6AD9I/OC11CBEJ3I/OY13A27I/OC6AD10I/OU9CCSJOY14TIO3I/OB6AD11I/OT10COEJOY15TIO5I/OA6AD12I/OE1DCJIY16TIO7I/OE7AD13I/OB8DEVSELJI/OY17MA6OD7AD14I/OE3EADSJOY18MA9OC7AD15I/OD9FRAMEJI/OY19MA11OB9AD16I/OH10GNDPY20----A9AD17I/OH11GNDPA1
----E10AD18I/OH12GNDPY20----D10AD19I/OH13GNDPH8GNDPW2HD11I/OH2HD61I/OH9GNDPW1HD12I/OH3HD62I/OJ10GNDPV3HD13I/OG1HD63I/OJ11GNDPV2HD14I/OE2HITMJIJ12GNDPV1HD15I/OF4HLOCKJIJ13GNDPU1HD16I/OE9IRDYJI/OJ8GNDPU2HD17I/OG4KENJOJ9GNDPU3HD18I/OD8LOCKJI/OK10GNDPU4HD19I/OV15MA2OK11GNDPU5HD20I/OW16MA3OK12GNDPT1HD21I/OV16MA4OK13GNDPT2HD22I/OU16MA5OK8GNDPT3HD23I/OY17MA6OK9GNDPT4HD24I/OW17MA7OL10GNDPT5HD25I/OV17MA8OL11GNDPR1HD26I/OY18MA9OL12GNDPR2HD27I/OW18MA10OL13GNDPR3HD28I/OY19MA11OL8GNDPR4HD29I/OT13MAA0OL9GNDPR5HD30I/OT14MAA1OM10GNDPP1HD31I/OU14MAB0OM11GNDPP2HD32I/OU15MAB1OM12GNDPP3HD33I/OP19MD0I/OM13GNDPP4HD34I/ON18MD1I/OM8GNDPP5HD35I/ON20MD2I/OM9GNDPN1HD36I/OM17MD3I/O 
						

							Major Chips Description2-33 Table 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeN10GNDPN2HD37I/OM19MD4I/ON11GNDPN3HD38I/OL16MD5I/ON12GNDPN4HD39I/OL18MD6I/ON13GNDPN5HD40I/OL20MD7I/ON8GNDPM1HD41I/OK17MD8I/ON9GNDPM2HD42I/OK19MD9I/OC14GNTJ0OM3HD43I/OJ16MD10I/OB14GNTJ1OM4HD44I/OJ18MD11I/OA14GNTJ2OM5HD45I/OJ20MD12I/OA15GNTJ3OL1HD46I/OH17MD13I/ON17GNTJ4OL2HD47I/OH19MD14I/OT9GWEJOL3HD48I/OG16MD15I/OK5HCLKINIL4HD49I/OG18MD16I/OT6HD0I/OL5HD50I/OG20MD17I/OU6HD1I/OK1HD51I/OF17MD18I/OW5HD2I/OK2HD52I/OF19MD19I/OV5HD3I/OK3HD53I/OE16MD20I/OY4HD4I/OK4HD54I/OE18MD21I/OW4HD5I/OJ1HD55I/OE20MD22I/OV4HD6I/OJ2HD56I/OD17MD23I/OY3HD7I/OJ3HD57I/OD19MD24I/OY2HD8I/OJ4HD58I/OC17MD25I/OY1HD9I/OJ5HD59I/OC19MD26I/OW3HD10I/OH1HD60I/OB18MD27I/OB20MD28I/OB16MPD1I/OW15TIO6I/OA19MD29I/OA16MPD2I/OY16TIO7I/OC16MD30I/OD15MPD3I/OT15TIO8I/OE15MD31I/OC15MPD4I/OT16TIO9I/OP18MD32I/OB15MPD5I/OT17TIO10I/OP20MD33I/OE14MPD6I/OA8TRDYJI/ON19MD34I/OD14MPD7I/OT12TWEJOM16MD35I/OU17MWEJI/OF14VCC_CPM18MD36I/OG5NAJOF15VCC_CPM20MD37I/OA7PARI/OF6VCC_BPL17MD38I/OE6PCIMRQJOG15VCC_CPL19MD39I/OE11PCLKINIG6VCC_APK16MD40I/OA2PHLDAJOP6VCC_APK18MD41I/OB2PHLDJIP15VCC_CPK20MD42I/OT19RASJ0OR14VCC_BP 
						

							2-34Service GuideTable 2-4M1531 Numerical Pin ListNo.NameTypeNo.NameTypeNo.NameTypeJ17MD43I/OT18RASJ1OR15VCC_CPJ19MD44I/OU20RASJ2OR7VCC_APH16MD45I/OU19RASJ3OR6VDD5PH18MD46I/OU18RASJ4ON15VDD5SPH20MD47I/OV20RASJ5OH4WRJIG17MD48I/OR16RASJ6O------G19MD49I/OR17RASJ7O------F16MD50I/OD13REQJ0I------F18MD51I/OC13REQJ1I------F20MD52I/OB13REQJ2I------E17MD53I/OA13REQJ3I------E19MD54I/ON16REQJ4I/O------D16MD55I/OE5RSTJI------D18MD56I/OE8SERRJI/O------D20MD57I/OF3SMIACTJI------C18MD58I/OC8STOPJI/O------C20MD59I/OP17SUSPENDJI------B19MD60I/OU12TIO0I/O------A18MD61I/OU13TIO1I/O------A20MD62I/OV14TIO2I/O------B17MD63I/OY14TIO3I/O------H5MIOJIW14TIO4I/O------A17MPD0I/OY15TIO5I/O------2.2.2 M1533
The M1533 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
This chip has Integrated System Peripherals (ISP) (2 x 82C59 and serial interrupt, 1 x 82C54),
advanced features (Type F and Distributed DMA) in the DMA controller (2 x 82C54), PS/2
keyboard/mouse controller, two-channel dedicated IDE master controller with Ultra-33
specification, System Management Bus (SMB), and two OpenHCI 1.0a USB ports.  The ACPI
(Advanced Configuration and Power Interface) and PCI 2.1 (Delayed Transaction & Passive
Release) specification have also been implemented.  Furthermore, this chip supports the
Advanced Programmable Interrupt Controller (APIC) interface for Multiple-Processors system.
The M1533 also supports the deep flexible green function for the best green system.  It can
connect to the ALi Pentium North Bridge (M1521/M1531/M1541) and ALi Pentium Pro North Bridge
(M1615) to provide the best system solution.  One eight-byte bidirectional line buffer is provided for
ISA/DMA master memory read/writes; one 32-bit wide posted write buffer is provided for PCI
memory write & I/O write (for audio) cycles to the ISA bus, to provide a PCI to ISA IRQ routing
table, and
level-to-edge trigger transfer.