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Acer Extensa 390 Service Guide

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    							Major Chips Description2-65 2.4.4.3 Bottom View: BGA Ball AssignmentsFigure 2-865555 BGA Ball Assignments (Bottom View) 
    						
    							2-66Service Guide2.4.4.4 Pin Functions
    Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionPCI Bus InterfaceC1RST#InLowReset. This input sets all signals and registers in
    the chip to a known slate. All outputs from the
    chip are tri-stated or driven to an inactive state.
    This pin is ignored during Standby mode
    (STNDBY# pin low). The remainder of the
    system (therefore the system bus) may be
    powered down if desired (all bus output pins
    are tri-stated in Standby mode).D2BCLKInHighBus Clock. This input provides the timing
    reference for all PCI bus transactions. All bus
    inputs except RESET# are sampled on the rising
    edge of BCLK. BCLK may be any frequency from
    DC to 33MHz.M1PARI/OHighParity. This signal is used to maintain even parity
    across AD031 and C/BE0-3#. PAR is stable and
    valid one clock after the address phase. For data
    phases PAR is stable and valid one clock after
    either IRDY# is asserted on a write transaction or
    TRDY# is asserted on a read transaction. Once
    PAR is valid, it remains valid until one clock after
    the completion of the current data phase (i.e.,
    PAR has the same timing as AD0-3I but delayed
    by one clock). The bus master drives PAR for
    address and write data phases; the target drives
    PAR for read data phases.K2FRAME#InLowCycle Frame. Driven by the current master to
    indicate the beginning and duration of an access.
    Assertion indicates a bus transaction is
    beginning (while asserted, data transfers
    continue); de-assertion indicates the transaction
    is in the final data phaseK1IRDY#InLowInitiator Ready. Indicates the bus masters ability
    to complete the current data phase of the
    transaction. During a write, IRDY# indicates valid
    data is present on AD0-3 1; during a read it
    indicates the master is prepared to accept data.
    A data phase is completed on any clock when
    both IRDY# and TRDY# are sampled then
    asserted (wait cycles are inserted until this
    occurs).K4TRDY#S/TSLowTarget Ready. Indicates the targets ability to
    complete the current data phase of the
    transaction. During a read, TRDY# indicates that
    valid data is present on AD0-3 1; during a write it
    indicates the target is prepared to accept data. A
    data phase is completed on any clock when both
    IRDY# and TRDY# are sampled then asserted
    (wait cycles are inserted until this occurs).L1STOP#S/TSLowStop. Indicates the current target is requesting
    the master to stop the current transaction. 
    						
    							Major Chips Description2-67 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionL4DEVSEL#S/TSLowDevice Select. Indicates the current target has
    decoded its address as the target of the current
    accessL2PERR#S/TSLowParity Error. This signal reports data parity errors
    (except for Special Cycles where SERR# is
    used). The PERR# pin is Sustained Tri-state. The
    receiving agent will drive PERR# active two
    clocks after detecting a data parity error PERR#
    will be driven high for one clock before being tri-
    stated as with all sustained tri state signals.
    PERR# will not report status until the chip has
    claimed the access by asserting DEVSEL# and
    completing the data phase.L3SERR#ODLowSystem Error. Used to report system errors
    where the result will be catastrophic (address
    panty error, data panty errors for Special Cycle
    commands, etc.). This output is actively driven
    for a single PCI clock cycle synchronous to BCLK
    and meets (he same setup and hold time
    requirements as all other bused signals. SERR#
    is not driven high by the chip after being
    asserted, but is pulled high only by a weak pull-
    up provided by the system. Thus, SERR# on the
    PCI bus may take two or three clock periods to
    fully return to an inactive state.Note:S/TS stands for Sustained Tri-state. These signals are driven by only one device at a time, are
    driven high for one clock before released, and are not driven for at least one cycle after being
    released by the previous device. A pull-up provided by the bus controller is used to maintain an
    inactive level between transactions. 
    All signals listed above are powered by BVCC and GND.  ROMOE# is powered by
    MVCC and GND. 
    						
    							2-68Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionU2
    T3
    R4
    T2
    U1
    R3
    T1
    R2
    R1
    P2
    N3
    P1
    N2
    M4
    M3
    N1
    J1
    J2
    H1
    J3
    J4
    H2
    G1
    H3
    G3
    F2
    E1
    F3
    D1
    E2
    F4
    E3AD0
    AD1
    AD2
    AD3
    AD4
    AD5
    AD6
    AD7
    AD8
    AD9
    AD10
    AD11
    AD12
    AD13
    AD14
    AD15
    AD16
    AD17
    AD18
    AD19
    AD20
    AD21
    AD22
    AD23
    AD24
    AD25
    AD26
    AD27
    AD28
    AD29
    AD30
    AD31I/O
    I/O
    I/O
     I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/OHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighPCI Address/Data Bus
    Address and data are multiplexed on the same
    pins. A bus transaction consists of an address
    phase followed by one or more data phases (both
    read and write bursts are allowed by the bus
    definition).
    The address phase is the clock cycle in which
    FRAME# is asserted (AD0-31 contain a 32-bit
    physical address) For l/O, the address is a byte
    address. For memory and configuration, the
    address is a DWORD address. During data
    phases AD0-7 contain the LSB and 24-31 contain
    the MSB. Write data is stable and valid when
    IRDY# is asserted; read data is stable and valid
    when TRDY# is asserted. Data transfers only
    during those clocks when both IRDY# and
    TRDY# are asserted.
    C/BE3-0     Command Type      Support0000Interrupt Acknowledge
    0001Special Cycle
    0010I/O ReadY
    0011I/O WriteY
    0100-reserved-
    0101-reserved-
    0110Memory ReadY
    0111Memory WriteY
    1000-reserved
    1001-reserved-
    1010Configuration ReadY
    1011Configuration WriteY
    1100Memory read Multiple
    1101Dual Address Cycle
    1110Memory Read Line
    1111Memory Read & InvalidateP3
    M2
    K3
    F1C/BE0#
    C/BE1#
    C/BE2#
    C/BE3#In
    In
    In
    inLow
    Low
    Low
    LowBus Command/Byte Enables. During the address
    phase of a bus transaction, these pins define the
    bus command (see list above). During the data
    phase, these pins are byte enables that
    determine which byte lanes carry meaningful
    data: byte 0 corresponds to AD07, byte 1 to 8-15,
    byte 2 to 16-23. and byte 3 to 2431G2IDSELInHighInitialization Device Select. Used as a chip select
    during configuration read and write transactionsNote:All signals listed above are powered by BVCC and GND. 
    						
    							Major Chips Description2-69 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionDisplay Memory InterfaceD18
    Cl9
    B20
    C18
    A20
    Bl9
    Al9
    B18
    C17
    D16AA0(CFG0)
    AAI(CFG1)
    AA2(CFG2)
    AA3(CFG3)
    AA4(CFG4)
    AA5(CFG5)
    AA6(CFG6)
    AA7(CFG7)
    AA8(CFG8)
    AA9(CFG9)I/O
    l/O
    l/O
    l/O
    l/O
    I/0
    l/O
    l/O
    l/O
    I/OBoth
    Both
    Both
    Both
    Both
    Both
    Both
    Both
    Both
    BothDRAM address bus for Bank 0 and Bank
    AA0 through AA9 also serve as configuration bits
    CFG0 through CFG9. Please see the
    descriptions for registers XR70 and XR71 for
    complete details on configurationD10
    A10
    B10
    C10
    A9
    B9
    A8
    C9
    B8
    A7
    C8
    B7
    A6
    C7
    B6
    A5MA0(TM0)
    MA1(TM1)
    MA2(CFG10)
    MA3(CFG11)
    MA4(CFG12)
    MA5(CFG13)
    MA6(CFG14)
    MA7(CFG15)
    MA8(RMD0)
    MA9(RMDI)
    MA10(RMD2)
    MA11(RMD3)
    MA12(RMD4)
    MA13(RMD5)
    MA14(RMD6)
    MA15(RMD7)I/O
    l/O
    l/O
    I/O
    l/O
    l/O
    l/O
    I/O
    l/O
    l/O
    I/O
    l/O
    l/O
    I/O
    l/O
    l/OHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighDRAM data bits 0-15.
    MA0 is also a test mode signal (Tri-Stale
    Enable).
    MA1 is also a test mode signal (ICT Enable).
    MA2 through MA7 also serve as configuration
    bits CFG10 through CFG15. Please see the
    description for register XR71 for complete details
    on configuration options.
    MA8 through MA15 are also serve as the data
    bus for the BIOS ROM during system startup
    (i.e., before the system enables the graphics
    controller memory interface).D15
    B16
    A17
    C15
    A16
    B15
    C14
    A15
    B14
    C13
    A14
    B13
    D12
    C12
    A13
    B12MB0(RMA0)
    MBI(RMAI)
    MB2(RMA2)
    MB3(RMA3)
    MB4(RMA4)
    MB5(RMA5)
    MB6(RMA6)
    MB7(RMA7)
    MB8(RMA8)
    MB9(RMA9)
    MB10(RMA10)
    MB11(RMA11)
    MB12(RMA12)
    MB13(RMA13)
    MB14(RMA14)
    MB15(RMA15)I/0
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    I/0
    l/O
    l/O
    l/O
    l/O
    l/O
    l/OHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighDRAM data bits 16-31.
    MB0 through MB15, along with MDI I and MD12,
    also serve as the address bus for the BIOS ROM
    during startup (i.e., before he system enables the
    graphics controller memory interface).
    Normally, a separate graphics BIOS ROM is not
    required in portable computer designs, because
    the graphics BIOS is normally placed in the
    same ROM devices as the system BIOS.
    However, this graphics controller provides this
    BIOS ROM interface capability for use in
    development systems and add-in cards for flat
    panel displays. Since the PCI bus specification
    requires only one load on the PCI bus for each
    PCI device, this BIOS ROM interface is provided
    to allow access to the BIOS ROM through the
    graphics controller chip, itself. 
    						
    							2-70Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionJ18
    J17
    H19
    G20
    H18
    G19
    F20
    G18
    F19
    D20
    E19
    F17
    E18
    D19MC0
    MC1
    MC2
    MC3
    MC4
    MC5
    MC6
    MC7
    MC8
    MC11
    MC12
    MC13
    MC14
    MC15I/0
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    I/0
    l/O
    l/O
    l/O
    l/OHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighDRAM data bits 32-47.R20
    P19
    N18
    P20
    N19
    M17
    M18
    N20
    M19
    M20
    L18
    L19
    L20
    L17
    K17
    K20MD0
    MD1
    MD2
    MD3
    MD4
    MD5
    MD6
    MD7
    MD8
    MD9
    MD10
    MD11(RMA16)
    MD12(rma17)
    MD13
    MD14
    MD15I/0
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    l/O
    I/0
    l/O
    l/O
    l/O
    l/O
    l/O
    l/OHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighDRAM data bits 48-63.
    MD11-12 are also ROM addresses 16-17.
    MD11 and MD12, along with MB0 through MB15,
    also serve as the address bus for the BIOS ROM
    during startup (i.e., beore the system enables the
    graphics controller memory interface).C11
    K18#RAS0#
    PAS1#Out
    OutLow
    LowRAS for DRAM Bank 0 (128K, 256K, or 512K by
    64-bit).
    RAS for DRAM Bank 1.C6ROMOE#(MCLKOUT)OutLowOutput Enable for BIOS ROM.  May be
    configured as MCLK output in test mode.D11
    A11
    C16
    B17
    H20
    J19
    P18
    R19ASAL#
    ASAH#
    CASBL#
    CASBH#
    ASCL#
    ASCH#
    ASDL#
    CASH#Out
    Out
    Out
    Out
    Out
    Out
    Out
    OutHigh
    High
    High
    High
    High
    High
    High
    HighCAS for dual-CAS EDO DRAM.
    Memory data byte mask signals. one mask
    signal for each of the eight data bytes in the 64-
    bit Qword. The masking is performed on a per-
    byte basis. A given byte is masked when the
    signal is high, or enabled when the signal is low.
    Masking is needed on write operations to specify
    which bytes in the 64-bit word are being written.B11WEA#OutLowMA[15:0] write enable for dual-CAS EDO DRAMA18WEB#OutLowMB[15:0] write enable for dual-CAS EDO DRAMJ20WEC#OutLowMC[15:0] write enable for dual-CAS EDO DRAMT20WED#OutLowMD[15:0] write enable for dual-CAS EDO DRAMNote:All signals listed above are powered by MVCC and GND.
    The 8 bytes comprising each 64-bit Qword are labeled AL, AH, BL, BH, CL, CH, DL, and DH.
    There is a separate byte mask signal for each byte. Up to two banks can be supported, with
    RAS0# controlling the first bank and RAS l# controlling the second bank. The address, data and
    byte mask signals are the same for each bank. 
    						
    							Major Chips Description2-71 Table 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionFlat Panel Display InterfaceW6
    V7
    Y6
    W7
    V8
    Y7
    W8
    U9
    V9
    Y8
    W9
    Y9
    V10
    W10
    Y10
    U10
    U11
    Y11
    W11
    V11
    Y12
    Y13
    V12
    U12
    W13
    Y14
    V13
    W14
    Y15
    V14
    W15
    Y16
    V15
    Y17
    W16
    U15P0
    P1
    P2
    P3
    P4
    P5
    P6
    P7
    P8
    P9
    P10
    P11
    P12
    P13
    P14
    P15
    P16
    P17
    P18
    P19
    P20
    P21
    P22
    P23
    P24
    P25
    P26
    P27
    P28
    P29
    P30
    P31
    P32
    P33
    P34
    P35Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    Out
    OutHigh
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    High
    HighFlat panel data bus of up to 36-bitsY5SHFCLKOutHighShift Clock. Pixel clock for nat panel dataW5FLMOutHighFirst Line Marker. Flat Panel equivalent of
    VSYNCY4LP
    (CL1)(DE)(BLANK#)OutHighLatch Pulse (may also be called CL1 ). Flat
    Panel equivalent of HSYNC. May also be
    configured as DE (display enable) or BLANK#
    outputV6M
    (DE)(BLANK#)OutHighM signal for panel AC drive control (may also be
    called ACDCLK). May also be configured as DE
    (display enable) or BLANK# outputV5
    W4
    U6ENAVDD
    ENAVEE(ENABKL)
    ENABKLI/O
    I/O
    I/Ohigh
    High
    HighPower sequencing control for panel driver
    electronics voltage VDD
    Power sequencing control for panel bias voltage
    VEE. May also be configured as ENABKL
    Power sequencing control for enabling the
    backlight. 
    						
    							2-72Service GuideTable 2-865555 Pin FunctionsBallPin NameTypeActiveDescriptionNote:All signals listed above are powered by DVCC and GND. 
    						
    							Major Chips Description2-73 Notes for table below:
    · To accommodate a wide variety of panel types, the graphics controller has been designed to output its
    data in any of a number of formats. These formats include different data widths for the colors belonging
    to each pixel, and the ability to accommodate different pixel data transfer timing requirements.
    · For STN-DD panels, pins PO through P35 are organized into groups corresponding to the upper and
    lower parts of the panel. The names of the signals for the upper and lower parts follow a naming
    convention of Uxx and Lxx, respectively.
    · For panels that require a pair of adjacent pixels be sent with every shift clock, pins PO through P35 are
    organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels
    being sent. The names of the signals for the first and second pixels of each such pair follow a naming
    convention of Fxx and Sxx, respectively.
    · Panels that transfer data on both edges of SHFCLK are also supported. See the description for register
    FR12 for more details.
    MonoMonoMonoColorColorColorColorColorColorColorColorColorSSDDDDTFTTFTTFTTFT HRSTN SSSTN SSSTN DDSTN DDSTN DDPin#Pin
    Name8-bit8=bit16 bit9/12/16bit18/24 bit36 bit18/24 bit8-it(4bP)8-bit(4bp)8-bit(4bp)8-bit(4bp)8-bitW6P0P0UD3UD7B0B0FB0FB0R1R1UR1UR0UR0V7P1P1UD2UD6B1B1FB1B1B1G1UG1UG0UG0Y6P2P2UD1UD5B2B2FB2FB2G2B1UB1UB0UB0W7P3P3UD0UD4B3B3FB3FB3R3R2UR2UR1LR0V8P4P4LD3UD3B4B4FB4SB0B3G2LR1LR0LG0Y7P5P5LD2UD2G0B5FB5SB1G4B2LG1LG0LB0W8P6P6LD1UD1G1B6SB0SB2R5R3LB1LB0UR1U9P7P7LD0LD0G2B7SB1SB3B5G3LR2LR1UG1V9P8--LD7G3G0SB2FG0-B3-UG1UB1Y8P9--LD6G4G1SB3FG1-R4-UB1LR1W9P10--LD5G5G2SB4FG2-G4-UR2LG1Y9P11--LD4R0G3SB5FG3-B4-UG2LB1V10P12--LD3R1G4FG0SG0-R5-LG1UR2W10P13--LD2R2G5FG1SG1-G5-LB1UG2Y10P14--LD1R3G6FG2SG2-B5-LR2UB2U10P15--LD0R4G7FG3SG3-R6-LG2LR2U11P16----R0FG4FR0----LG2Y11P17----R1FG5FR1----LB2W11P18---R2SG0FR2----UR3V11P19----R3SG1FR3----UG3Y12P20----R4SG2SR0---UB3Y13P21----R5SG3SR1----LR3V12P22----R6SG4SR2----LG3U12P23----R7SG5SR3----LB3W13P24-----FR0------Y14P25-----FR1------V13P26-----FR2------W14P27-----FR3------Y15P28-----FR4------V14P29-----FR5------W15P30-----SR0------Y16P31-----SR1------V15P32-----SR2------Y17P33-----SR3------W16P34-----SR4------U15P35-----SR5------Y15SHFCLKSHFCLK
    SHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKSHFCLKPixels/Clock:881611222-2/35-1/32-2/35-1/38 
    						
    							2-74Service GuideTable 2-865555 Pin Functions (continued)BallPin NameTypeActiveDescriptionCRT InterfaceU3HYSNC(CSYNC)OutBothCRT Horizontal Sync (polarity is programmable) or
    Composite Sync for support of various external
    NTSC/PAL encoder chipsV2VSYNCOutBothCRT Vertical Sync (polarity is programmable)Y3
    V4
    W3RED
    GREEN
    BLUEOut
    Out
    OutAnalog
    Analog
    AnalogCRT analog video outputs from the internal color
    palette DAC. The DAC is designed for a 37.5S2
    equivalent load on each pin (e.g. 75Q resistor on
    the board, in parallel with the 75D CRT load)W2RSETInN/ASet point resistor for the internal color palette DAC.
    A 560 Q 1% resistor is required between RSET and
    AGNDV3
    U4DDC
    DATA(GPIO2)
    DDC CLK(GPIO3)I/O
    I/OHigh
    HighGeneral purpose I/0, suitable for use as DDC data.
    General purpose I/0, suitable for use as DDC
    DATA. These two pins are functionally suitable for a
    DDC interface between the 65555 and a CRT
    monitorNote:HSYNC, VSYNC, GPIO2, and gpio3 are powered by CVCC and GND.  RED, GREEN, BLUE and
    RSET are powered by AVCC and AGND.Power/Ground and Standby ControlU5AVCCVCC-Analog power and ground pins for noise isolation
    for the internal color palette DAC. AVCC should be
    isolated from digital VCC as described in the
    Functional Description of the internal color palette
    DAC. For proper DAC operation, AVCC should not
    be greater than IVCC. AGND should be common
    with digital ground but must be lightly decoupled to
    AVCC. See the Functional Description of the
    internal color palette DAC for further informationB3
    A2
    C4,D5
    A3, B4
    W1SVCC
    SGND
    PVCC
    PGND
    CVCCVCC
    GND
    VCC
    GND
    VCC-
    -
    -Analog power and ground pins for noise isolation
    for the internal clock synthesizer (for MCLK). Must
    be the same as IVCC, 3.3V.
    Analog power and ground pins for noise isolation
    for internal clock synthesizer (for VCLK). Must be
    the same as IVCC.
    SVCC/SGND and PVCC/PGND pairs must be
    carefully decoupled individually. Refer also lo the
    section on clock ground layout in the Functional
    Description.
    Power for CRT Interface, 3.3V.D9, &
    W12
    D14
    D7
    G17
    G4,
    P17IVCC
    GNDVCC
    GND-
    -Power/Ground (Internal Logic), 3.3V. Note that this
    voltage must be the same as SVCC and PVCC
    (voltages for internal clock synthesizers) 
    						
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