Acer Extensa 390 Service Guide
Have a look at the manual Acer Extensa 390 Service Guide online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 720 Acer manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
Major Chips Description2-5 2.1.3 Terminal Functions This section describes the PCI1250A terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc. for quick reference. The terminal numbers are also listed for convenient reference. Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPower Supply TerminalsGNDA01, D04, D08, D13, 17, H04, H17, N04, N17, U04, U08, U13, U17,IDevice ground terminalsVCCD06, D11, D15, F04, F17, 04, L17, R04, R17, U06, U10, U15I3.3 V Power supply terminal for core logic.VCCAK02, R03, W05IRail Power Input for PC Card A Interface. Indicates Card A signaling environment.VCCBB16, C10, F18IRail Power Input for PC Card B Interface. Indicates Card A signaling environment.VCCIV10IRail power Input for interrupt subsystem interface and miscellaneous l/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT. PCREQ SUSPENCX, SPKROUT, GPI01:0, IRQMUX7:0, INTA, INTB CLOCK. DATA, LATCH, and RI_OUTVCCPK20, P18, V15, W20IRail power input for PCI signaling.VCCZA04, D01IRail power input for the Zoom Video InterfacePCI System TerminalsPCLKJ17IPCI bus clock. Provides timing fot all transactions on the PCI bus. All PCI signals are sampled at the rising edge H PCLK.PRSTJ19IPCI reset When the PCI bus reset is asserted the PRST signal causes the PCI 1 250A to 3-state all output buffers and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1250A is in its default state. When the SUSPEND mode is enabled, the device is protected from the PRST clearing the internal registers. An outputs are 3-statea but the contents of the registers are preservedCLKRUNJ18OPCI clock run. This signal is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1250A responds accordingly.
2-6Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPCI Address and Data TerminalsAD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0K18 K19 L20 L18 L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14PCI address data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31:0 contain a 32-bit address or other destination. During the data phase AD31 0 contain data.C/BE3 C/BE2 C/BE1 C/BE0M17 T20 W19 Y17I/OPCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During address phase of a primary bus PCI cycle, C/BE3:0 define the bus command. During the data phase, this four-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7:0), C/BE1 applies to byte 1 (AD15:8), C/be2 applies to byte 2 (AD23:16) and C/BE3 applies to byte 3 (AD31:24).PARY20I/OPCI bus party In all PCI bus read and write cycles the PCI1250A calculates even parity across the AD31:0 and C/BE3:0 buses. As an initiator during PCI cycles, the PCI1250A outputs this parity indicator with a one PCLK delay. As a target during PCI cycles. the calculated parity is compared to the initiators parity indicator. A miscompare can result in the assertion of a parity error (PERR).
Major Chips Description2-7 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPCI Interface Control TerminalsDEVSEV20I/OPCI device select. The PCI1250A asserts this signal to claim a PCI cycle as the target device. As a PCI initiator on the bus. the PCI1250A monitors this signal until a target responds. If no target responds before time-out occurs, then the PCI1250A will terminate the cycle with an initiator abort.FRAMET19I/OPCI cycle frame. This signal is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasseerted the PCI bus transaction is in the final data phase.GNTJ20IPCI bus grant. This signal is driven by the PCI bus arbiter to grant the PCI1250A access to the PCI bus after current data transaction has completed. This signal may or may not follow a PCI bus request depending upon the PCI bus parking algorithm.GPIO2/LOCKV19I/OPCI bus general purpose l/O pins or PCI bus lock. These pins are can be configured as PCI LOCK and used to gain exclusive access downstream. Since this functionality is not typically used, a general purpose I/O may be accessed through this terminal. This terminal defaults to a general purpose input, and maybe configured through the GPIO2 Control RegisterIDSELN20IInitalization device select. IDSEL selects the PCI1250A during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.IRDYT18I/OPCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted. wait states are inserted.PERRU18I/OPCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PAR, when PERR is enabled through bit 6 of the command register.REQK17OPCI bus request. Asserted by the PCI1250A to request access to the PCI bus as an initiator.SERRU19OPCI system error. Output that is pulsed from the PCI1250A, when enabled through the command register, indicating a system error has occurred. The PCI 1250A needs not be the target of the PCI cycle in order to assert this signal. When SERR is enabled in the control register, this signal will also pulse indicating that address parity error has occurred on a CardBus interface.
2-8Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSTOPT17I/OPCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus tranaction. This signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers.TRDYU20I/OPCI target ready. TRDY indicates the primary bus target s ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.PC Card 16 Address And Data Terminals (Slot A And Slot B)Slot A1 Slot B2A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0T04 U02 U01 P04 R02 R01 P01 N02 M04 T01 T02 P02 N03 T03 M01 L01 M03 N01 V01 V02 V03 W02 W03 W04 V04 U05C14 B15 C15 C16 A18 C17 B18 A20 C18 A17 A16 B17 A19 D14 D18 E18 B20 B19 A15 A14 B13 A13 C12 A12 B11 C11OPC Card Address 16-bit PC Card address lines. A25 is the most significant bit 1 Terminal name for slot A is preceded with A_. For example, the full name for terminal T04 is A_A25. 2 Terminal name for slot B s preceded with B_. For example, the full name for terminal C14 is B_A25.
Major Chips Description2-9 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0K03 J02 J04 H02 G01 W08 Y07 V07 J01 J03 H01 H03 G02 V08 W07 Y06E19 E20 G18 G19 H18 B07 C08 A08 G17 F19 F20 F19 H19 A07 B08 D09I/OCard Data. 16-bit PC Card data lines. D15 is the most significant16-Bit PC Card Interface Control Terminals (Slot A And Slot B)Slot A3 Slot B4BVD1 (STSCHG/RI)V06A09Battery Voltage Detect 1. Generated by 16-bitmemory PC Cards that include batteries. BVD1 isused with BVD2 as an indication of the condition ofthe batteries on a memory PC Card. Both BVD1and BVD2 are kept high when the battery is good.When BVD2 is low and BVD1 is high, the battery isweak and needs to be replaced. When BVD1 islow, the battery is no longer serviceable and thedata in the memory PC Card is lost. See the CardStatus Change interrupt Configuration register forenable bits. See the Card Status Change registerand the Interface Status register for the status bitsfor this signal.Status Change (STSCHG). STSCHG is used toalert the system to a change in the READY, writeprotect, or battery voltage dead condition of a 16- bit l/O PC Card. Ring Indicate (RI). Ring indicate is used by 16-bit modem cards to indicate a ring detection. 3 Terminal name for slot A is preceded with A_. For example, the full name for terminal W01 is A_ESET 4 Terminal name for slot B s preceded with B_. For example, the full name for terminal B13 is B_RESET
2-10Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionBVD2 (SPKR)Y05D10IBattery Voltage Detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the Card Status Change Interrupt Configuration Register for enable bits. See the Card Status Change register and the Interface Status register for the status bits for this signal. Speaker (SPKR) Speaker is an optional binary audio signal available only when the card and socket have been configured: for the 16-bit l/O interface. The audio signals from cards A and B are combined by the PCI 1250A and are output on the SPKROUT pin. DMA Request.: This pin may be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts this signal to indicate a request for a DMA operation.CD1 CD2G03 W06H20 C09IPC Card Detect 1 and Card Detect 2. CD1 and CD2 are connected to ground internally on the PC Card. When a PC Card is inserted into a socket. these signals are pulled low. The signal status is available by reading the interface status registerCE1 CE2K01 L02D20 D19OCard Enable 1 and Card Enable 2. These signals enable even and odd numbered address bytes. CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes.INPACKY01D12IInput acknowledge. This signal is asserted by the PC Card when it can respond to an l/O read cycle at the current address. DMA Request. This pin may be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.IORDL04E17OI/O read. IORD is asserted by the PCI1250A to enable 16-bit t/O PC Card data output during host l/O read cycles. DMA Write. This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card which supports DMA. The PCI1250A asserts this signal during DMA transfers from the PC Card to host memory.
Major Chips Description2-11 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionIOWRM02C19OI/O Write IOWR is driven low by the PCI1250A to strobe write data into 16-bit l/O PC Cards during host l/O write cycles. DMA Read. This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1250A asserts this signal during transfers from host memory to the PC Card.OEL03C20OOutput Enable. OE is driven low by the PCl1250A to enable 16-bit Memory PC Card data output during host memory read cycles. DMA terminal count. This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PCI1250A asserts this signal to indicate terminal count for a DMA write operationREADY/IREQY04A10IThe ready function is provided by the READY signal when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit Memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit Memory PC Card is ready to accept a new data transfer command. Interrupt Request. IREQ is asserted by a 16-bit l/O PC Card to indicate to the host that a device on the 16-bit l/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.REGY02B12OAttribute memory select. REG remains high for all common memory accesses. When REG is asserted access is limited to attribute memory (OE or WE active) and to 1he l/O space (IORD or IOWR active}. Attribute memory is a separately accessed section of card memory and is generally use to record card capacity and other configuration and attribute information. DMA acknowledge. This pin is used as a DACK during DMA operations to a 16-bit PC Card that supports DMA. The PCI1250A asserts this signal to indicate a DMA operation. This signal is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.RESETW01C13OPC Card reset. RESET forces a hard reset to a 16- bit PC CardWAITV05B10IBus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e.. extend) the memory or l/O cycle that is in progress.
2-12Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionWEP03D16OWrite enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also use for memory PC Cards that employ programmable memory technologies. DMA terminal count. This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PC1031 asserts this signal to indicate terminal count for a DMA read operation.WP (IOIS16)U07B09IWrite protect. This signal applies to 16-bit memory PC Cards. WP reflects the status of the write- protect switch on 16-bit memory PC Cards. For 16- bit l/O cards, WP is used for the 16-bit port (IOSI16) function. IOIS16 (I/O is 16-bits). This signal applies to 16-bit l/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds and the l/O port that is addressed is capable of 16- bit accesses. DMA request. This pin can be used as the DMA request signal during DMA operations to a 16-bit PC Card which supports DMA. If used, the PC Card asserts this signal to indicate a request for a DMA operationVS1 VS2Y03 U03A11 B14I/OVoltage Sense 1 and Voltage Sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card.Cardbus PC Card Interface System TerminalsSlot A5 Slot B6CCLKT01A17OCardBus PC Card Clock. This signal provides synchronous timing for all transactions on the ] CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG. CAUDIO, CCD2:1, and CVS2.1 are sampled on the rising edge of the CCLK, and all timing parameters are defined with the rising edge of this signal. The CardBus clock operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. 5 Terminal name for slot A is preceded with A_. For example, the full name for terminal N03 is A_CPAR. 6 Terminal name for slot B s preceded with B_. For example, the full name for terminal A19 is B_CPAR.
Major Chips Description2-13 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCRSSTW01C13I/OCardBus PC Card Reset. This signal is used to bring CardBus PC Card specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-statedt and the PCI1250A will drive these signals to a valid logic level. Assertion may be asynchronous to the CCLK. But deassertion must be synchronous to the CCLK.CCLKRUNU07B09OCardBus PC Card Clock Run. This signal is used by a CardBus PC Card to request an increase in the CCLK frequency. and the PCI 1 250A to indicate that the CCLK frequency will be decreased.CardBus PC Card Address and Data Terminals (Slot A and Slot B)CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 C AD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0W08 Y07 W07 V07 Y06 U05 V04 W04 W03 W02 V03 V02 T04 V01 U02 M04 M02 M03 L04 M01 L03 L02 L01 K03 J01 J04 J03 H02 H01 G01 H03 G02B07 C08 B08 A08 D09 C11 B11 A12 C12 A13 B13 A14 C14 A15 B15 C18 C19 B20 E17 D18 C20 D19 E18 E19 G17 G18 F19 G19 F20 H18 G20 H19I/OPC Card Address and Data bus. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31:0 contain a 32- bit address. During the data phase of a CardBus cycle, CAD31:0 contain data. CAD31 is the most significant bit
2-14Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCC/BE3 CC/BE2 CC/BE1 CC/BE0Y02 T03 N01 K01B12 D14 B19 D20I/OCardBus Bus Commands and Byte Enables. The command and byte enable signals are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3:0 defines the bus command. During the data phase, this four-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32- bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7:0), CC/BE1 applies to byte 1 (CAD15:8), CC/BE2 applies to byte 2 (CAD23:8), and CC/BE3 applies to byte 4(CAD31:24)CPARN03A19I/OCardBus Parity. In all CardBus read and write cycles, the PCl1250A calculates even parity cross the CAD and CC/BE buses. As an initiator during CardBus cycles, the PC11250A outputs this parity indicator with a one CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiators parity indicator; a miscompare can result in a parity error assertion.Cardbus Interface Control TerminalsSlot ASlot BCAUDIOY05D10ICardBus Audio. This signal is a digital input signal from a PC Card to the system speaker. The PCI1250A supports the binary audio mode, and outputs a binary signal from the card to the SPKROUT signalCBLOCKP01B18I/OCardBus Lock. This signal is used to gain exclusive access to a targetCCD1 CCD2G03 W06H20 C09ICardBus Detect 1 and CardBus Detect 2. These signals are used in conjunction with voltage sense signals to identify ca d insertion and interrogate cards to determine the operating voltage and card type.CDEVSELR02A18I/OCardBus device select. The PCI1250A asserts this signal to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1250A monitors this signal until a target responds. If no target responds before time-out occurs, then the PCI1250A will terminate the cycle with an initiator abort.CFRAMEU01C15I/OCardBus cycle frame. This signal is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning. and data transfers continue while this signal is asserted. When CFRAME is deasserted the CardBus bus transaction is in the final data phase.CGNTP03D16ICardBus bus grant. This signal is driven by the PCI1250A to grant a CardBus PC Card access to the CardBus bus after ihe current data transaction has completed.