Acer Extensa 390 Service Guide
Have a look at the manual Acer Extensa 390 Service Guide online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 720 Acer manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
Major Chips Description2-15 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCINTY04A10ICardBus interrupt. This signal is asserted low by a CardBus PC Card to request interrupt servicing from the host.CIRDYT02A16I/OCardBus initiator ready. CIRDY indicates the CardBus initiators ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of CCLK where both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.CPERRP02B17I/OCardBus Parity Error. This signal is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.CREQY01D12ICardBus Request. This signal indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiatorCSERRV05B10ICardBus System Error. This signal reports address parity errors and other system errors which could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK but ceasserted by a weak pull-up, and may take a few CCLK periods. The PCI1250A can report CSERR to the system by assertion of SERR on the PCI interface.CSTOPR01C17I/OCardBus Stop Signal. This signal is driven by a CardBus target to request the initiator to stop the current CardBus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers.CSTSCHGV06A09ICardBus Status Change. CSTSCHG is used to alert the system to a change in the cards status, and is used as a wake-up mechanism.CTRDYP04C16I/OCardBus Target Ready. CTRDY indicates the CardBus targets ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of CCLK where both CIRDY and CTRDY are asserted; until which wait states are insertedCVS1 CVS2Y03 U03A11 B14I/OCardBus Voltage Sense 1 and Voltage Sense 2. These signals are used in conjunction with card detect signals to identify card insertion and interrogate cards to determine the operating voltage and card type.
2-16Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSystem Interrupt TerminalsGPIO3/INTAV13I/OGPI03/lNTA Parallel PCI Interrupt. This terminal can be connected to an available PCI interrupt if parallel PCI interrupts are used, and the PCI1250A will output PCI INTA through this terminal. Refer to the Interrupt Subsystem description in this document for details on interrupt signaling. This terminal defaults to a general purpose inputIRQSER/INTBW13I/OIRQSER Serial Interrupt Signal / INTB Parallel PCI Interrupt. When this terminal is configured as IRQSER, it provides the IRQSER style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. This terminals can be configured as the parallel PCI INTB interrupt. Refer to the Interrupt Subsystem description in this document for details on interrupt signaling. This terminal defaults to the IRQSER signal since this is the default interrupt signaling methodIRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0Y12 U11 W10 Y09 W09 V09 U09 Y08OThe primary function of these terminals is to provide the ISA type IRQ signaling supported by the PCl1250A. These Interrupt mux outputs can be mapped to any of 15 IRQs. The Device Control register must be programmed for the ISA IRQ interrupt mode and the IRQMUX Routing Register must have the IRQ routing programmed before these terminals are enabled. All of these terminals have secondary functions, such as PC/PCI DMA request/grant, ring indicate output, and zoom video status. that can be selected; with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing. See the IRQMUX Routing register for programming optionsRI-OUT/PMEY13ORing indicate Output/Power Management Event. RI_OUT allows the RI input from one of the PC Cards to pass through o the system. This pin is the RI_OUT signal when the PCI1250A is in the D0 (fully on) state and provides the PME signal when the device is in a D1, D2, or D3 state. IRQMUX4 or IRQMUX3 can be used to route the RI_OUT signal when the PME signal is routed on pin Y13 and a PC Card requires a ring indicate signalPC Card Power Switch TerminalsLATCHW13O3-Line power Switch latch. This signal is asserted by the PCI1250A to indicate to the PC Card power switch that the data on the DATA line is valid.
Major Chips Description2-17 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionCLOCKU12I/O3-Line Power Switch Clock. Information on the DATA line is sampled at the rising edge of CLOCK. This terminal defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the I/O System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2MHz. If a system design defines this terminal an output, then this terminal requires an external pull-up resister. The frequency of the PCI1250A output CLOCK is derived from dividing the PCI CLK by 36DATAV12O3-Line Power Switch Data. This signal is used to serially communicate socket power control information to the power switch.Zoomed Video TerminalsI/O and Memory Interface SignalZV_HREFA06A10OHorizontal Sync to the zoom video port.ZV_VSYNCC07A11OVertical sync to the zoom video port.ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0A03 B04 C05 B05 C06 D07 A05 B06A20 A14 A19 A13 A18 A8 A17 A9OVideo data to the zoom video port in YV:4:2:2 format.D02 C03 B01 B02 A02 C04 B03 D05D02 C03 B01 B02 A02 C04 B03 D05A25 A12 A24 A15 A23 A16 A22 A21OVideo data to the zoom video port in YV:4:2:2 format.ZV_SCLKC02A7OAudio SCLK PCM signal.ZV_MCLKD03A6OAudio MCLK PCM signal.ZV_PCLKE01IOIS16OPixel clock (PCLK) to the zoom video port.ZV_LRCLKE03INPACKOAudio LRCLK PCM signal.ZV_SDATAE02SPKROAudio PCM data signal (SDATA)ZV_RSVDF1 F2 F3 G4OReserved. No connection.ZV_RSV1 ZV_RSV0C1 E4A5 A4OReserved. No connection in PC Card. These signals are put into a high-impedance state by the host adapter.
2-18Service GuideTable 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionPC/PCI DMA TerminalsPCREQ/ IRQMUX7Y12OPC/PCI DMA Request. This signal is used to request DMA transfers as DREQ in a system supporting the PC. PCI DMA scheme. IRQMUX7. When this terminal is configured for IRQMUX7, it provides the IRQMUX7 interrupt output of the interrupt mux, and can be mapped to any of 15 ISA type IRQs. The IRQMUX7 signal takes precedence over PCREQ, and should not be enabled in a system using PC/PCI DMA. This pin is also used for the serial EEPROM interface.PCGNT/ IRQMUX6U11I/OPC/PCI DMA Grant. This signal is used to grant the DMA channel to a requester in a system supporting the pr PCI DMA scheme. IRQMUX6. When :his terminal is configured for IRQMUX6, it provides the IRQMUX6 interrupt output of the interrupt mux, and can be mapped to any of 15 ISA type IRQs. The IRQMUX6 signal takes precedence over PCGNT, and should not be enabled in a system using PC/PCI DMA. This pin is also used for the serial EEPROM interface.Miscellaneous TerminalsGPIO0/ LEDA1V11I/OGPIO0 / Socket Activity LED Indicator 1. When this signal is configured as LEDA1 it provides an output indicating PC Card socket O activity. Otherwise, this signal can be configured as a general purpose input and output, GPIO0. The zoom video enable signal (ZVSTAT) can also be routed to this signal through the GPIO0 Control register. This terminal defaults to a general purpose input.GPIO1/ LEDA2W11I/OGPI01 / Socket Activity LED Indicator 2. When this signal is configured as LEDA2 it provides an output indicating PC Card socket 1 activity. Otherwise, this signal can be configured as a general purpose input and output. GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. Refer to the GPI01 Control resister for programming details. This terminal defaults to a general purpose input.SUSPENDY1ISuspend. This signal is used to protect the internal registers from clearing when the PRST signal is asserted. For details on implementing SUSPEND in your system power management scheme refer to the section on SUSPEND mode.
Major Chips Description2-19 Table 2-2PCI1250 Terminal FunctionsNameNo.I/O TypeFunctionSPKROUTY10OSpeaker Output. This signal is the output to the host system that can carry the SPKR or CAUDIO signal through the PCI1250A from the PC Card interface. This signal is driven as the exclusive OR combination of card SPKR//CAUDIO inputs.
2-20Service Guide2.2 Aladdin IV (M1531/M1533) The Aladdin-IV is the succeeding generation chipset of Aladdin-III from Acer Labs. It maintains the best system architecture (two-chip solution) to achieve the best system performance with the lowest system cost (TTL-free). The Aladdin-IV consists of two BGA chips to give the 586-class system a complete solution with most up-to-date features and architecture for multimedia/ multithreading OS and software applications. It utilizes the modern BGA package to improve the AC characterization, resolves system bottleneck and makes the system manufacturing easier. 2.2.1 M1531 The M1531 includes: · Higher CPU bus frequency (up to 83.3 MHz) interface for the incoming Cyrix M2 and AMD K6, PBSRAM and Memory Cache L2 controller · Internal MESI tag bits (8K x 2) to reduce cost and enhance performance · High-performance FPM/EDO/SDRAM DRAM controller · PCI 2.1 compliant bus interface · Smart deep buffer design for CPU-to-DRAM, CPU-to-PCI, and PCI-to-DRAM to achieve the best system performance · Highly efficient PCI fair arbiter · The most flexible 32/64-bit memory bus interface for the best DRAM upgrade ability and ECC/parity design to enhance the system reliability With the concurrent bus design, PCI-to-PCI access can run concurrently with CPU-to-L2 and CPU- to-DRAM access, while PCI-to-DRAM access can run concurrently with CPU-to-L2 access. The M1531 also supports the snoop ahead feature to achieve the PCI master full-bandwidth access (133 MB) and provides the enhanced power management features including ACPI support, suspend DRAM refresh, and internal chip power control to support the Microsoft’s On Now technology OS. The M1533 offers the best power management system solution. It integrates ACPI support, deep green function, two-channel dedicated Ultra-33 IDE master controller, two-port USB controller, SMBus controller, and PS2 keyboard/mouse controller. The M1543 provides the best desktop system solution. It integrates ACPI support, green function, two-channel dedicated Ultra-33 IDE Master controller, two-port USB controller, SMBus controller, PS/2 keyboard/mouse controller and the Super I/O (Floppy Disk Controller, two serial port/one parallel port) support. The Aladdin-IV gives a highly-integrated system solution and a most up-to-date architecture to provide the best cost/performance system solution for desktop and notebook vendors.
Major Chips Description2-21 2.2.1.1 Features · Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz at 3.3V/2.5V · Supports Linear Wrap mode for Cyrix M1 and M2 · Write-Allocation feature for K6 · Pseudo-Synchronous PCI bus access (CPU bus: 75 MHz - PCI bus: 30 MHz, CPU bus: 83.3 MHz - PCI bus: 33 MHz) · Supports Pipelined-burst SRAM/Memory Cache · Direct mapped, 256 KB/512 KB/1 MB · Write-Back/Dynamic-Write-Back cache policy · Built-in 8K x 2 bit SRAM for MESI protocol to reduce cost and enhance performance · Cacheable memory up to 64 MB with 8-bit Tag SRAM · Cacheable memory up to 512 MB with 11-bit Tag SRAM · 3-1-1-1-1-1-1-1 for Pipelined-burst SRAM/Memory Cache at back-to-back burst read and write cycles · 3.3V/5V SRAMs for Tag address · CPU single-read cycle L2 allocation · Supports FPM/EDO/SDRAM DRAMs · 8 RAS lines up to 1 GB support · 64-bit data path to memory · Symmetrical/Asymmetrical DRAMs · 3.3V or 5V DRAMs · Duplicated MA[1:0] driving pins for burst access · No buffer needed for RASJ and CASJ and MA[1:0] · CBR and RAS-only refresh for FPM · CBR and RAS-only refresh and Extended refresh and self refresh for EDO · CBR and Self refresh for SDRAM · 16 Qword deep merging buffer for 3-1-1-1-1-1-1-1 posted-write cycle to enhance high- speed CPU burst access · 6-3-3-3-3-3-3-3 for back-to-back FPM read page hit, 5-2-2-2-2-2-2-2 for back-to-back EDO read page hit, 6-1-1-1-2-1-1-1 for back-to-back SDRAM read page hit, 2-2-2-2 for retired data for posted write on FPM and EDO page-hit, x-1-1-1 for retired data for posted write SDRAM page-hit · Enhanced DRAM page miss performance · Supports 64 Mbit (16M x 4, 8M x 8, 4M x 16) technology of DRAMs · Supports Programmable-strength RAS/CAS/ MWEJ/MA buffers · Supports Error Checking and Correction (ECC) and Parity for DRAM
2-22Service Guide· Supports the most flexible six 32-bit populated banks of DRAM for easy DRAM upgrade · Supports SIMM and DIMM · Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI interface · Concurrent PCI architecture · PCI bus arbiter: five PCI masters and M1533/ M1543 (ISA Bridge) supported · 6 DWords for CPU-to-PCI memory write posted buffers · Converts back-to-back CPU to PCI memory write to PCI burst cycle · 38/22 Dwords for PCI-to-DRAM Write-posted/ Read-prefetching buffers · PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back) · L1/L2 pipelined-snoop ahead for PCI-to-DRAM cycle · Supports PCI mechanism #1 only · Complies with PCI spec. 2.1 (N(32/16/8)+8 rule, passive release, fair arbitration) · Enhanced performance for Memory-Read-Line, Memory-Read-Multiple and Memory-write- Invalidate PCI commands · Enhanced Power Management · ACPI support · PCI bus CLKRUN function · Dynamic Clock Stop · Power-on Suspend · Suspend to Disk · Suspend to DRAM · Self refresh during Suspend · 328-pin (27mm x 27mm) BGA package
Major Chips Description2-23 2.2.1.2 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A NCPHLDAJAD3AD6AD8AD12PARTRDYJ AD17AD22 AD25AD30REQJ3 GNTJ2GNTJ3MPD2MPD0 MD61 MD29 MD62 B BEJ0PHLDJAD2AD5AD7AD11CBEJ1 DEVSELJ AD16AD21AD24AD29REQJ2 GNTJ1MPD5 MPD1 MD63 MD27 MD60 MD28 C BEJ3BEJ2BEJ1AD4 CBEJ0AD10AD15 STOPJCBEJ2 AD20CBEJ3AD28REQJ1 GNT0JMPD4 MD30 MD25MD58 MD26MD59 D BEJ6BEJ5BEJ4AD0AD1AD9AD14 LOCKJ FRAMEJAD19AD23 AD27REQJ0MPD7MPD3MD55MD23MD56 MD24MD57 E DCJHITMJEADSJBEJ7RSTJ PCIMRQJAD13 SERRJIRDYJAD18PCLKINAD26AD31MPD6 MD31MD20MD53MD21MD54 MD22 FBRDYJBOFFJ SMIACTJ HLOCKJADSJVCC_B VCC_CVCC_CMD50 MD18 MD51 MD19 MD52 G HD63CACHEJAHOLDKENJNAJVCC_A M1531VCC_C MD15 MD48MD16 MD49MD17 H HD60HD61HD62 WRJMIOJGNDGNDGNDGNDGNDGNDMD45 MD13MD46 MD14 MD47 J HD55HD56HD57HD58HD59 GNDGNDGNDGNDGNDGNDMD10 MD43 MD11MD44MD12 K HD51HD52HD53 HD54HCLKINGNDGNDGNDGNDGNDGNDMD40 MD8MD41 MD9MD42 L HD46HD47HD48 HD49HD50 GNDGNDGNDGNDGNDGNDMD5MD38MD6 MD39MD7 M HD41HD42HD43HD44HD45 GNDGNDGNDGNDGNDGNDMD35 MD3MD36 MD4MD37 N HD36HD37HD38HD39HD40 GNDGNDGNDGNDGNDGNDVDD5S REQJ4GNTJ4 MD1MD34MD2 P HD31HD32HD33 HD34HD35VCC_AVCC_C 32K SUSPENDMD32 MD0MD33 RHD26 HD27HD28 HD29HD30VDD5VCC_A VCC_BVCC_C RASJ6RASJ7 CASJ2CASJ7CASJ3 T HD21HD22HD23 HD24 HD25HD0A12A5GWEJ COEJCADVJ TWEJMAA0MAA1TIO8TIO9TIO10 RASJ1RASJ0CASJ6 U HD16HD17HD18 HD19HD20HD1A13A8CCSJBWEJCADSJTIO0TIO1MAB0MAB1MA5MWEJRASJ4RASJ3RASJ2 V HD15HD14HD13 HD6HD3A17A14A10A4 A29A25A24A23TIO2MA2MA4MA8 CASJ5CASJ1RASJ5 W HD12HD11 HD10HD5HD2A18A15A11A7A30A31A22A21TIO4TIO6MA3MA7MA10 CASJ0 CASJ4 Y HD9HD8HD7HD4A20A19A16A9A6A3A28A26A27TIO3TIO5TIO7MA6MA9MA11 NCFigure 2-2M1531 Pin Diagram (Top View)
2-24Service Guide2.2.1.3 Signal Descriptions Table 2-3M1531 Signal DescriptionsSignalTypeDescriptionHost Interface 3.3V/2.5VA[31:3]I/O Group AHost Address Bus Lines. A[31:3] have two functions. As inputs, along with the byte enable signals, these pins serve as the address lines of the host address bus which define the physical area of memory or I/O being accessed. As outputs, the M1531 drives them during inquiry cycles on behalf of PCI masters.BEJ[7:0]I Group AByte Enables. These are the byte enable signals for the data bus. BEJ[7] applies to the most significant byte and BEJ[0] applies to the least significant byte. They determine which byte of data must be written to the memory, or are requested by the CPU. In local memory read and line-fill cycles, these inputs are ignored by the M1531.ADSJI Group AAddress Strobe. The CPU will start a new cycle by asserting ADSJ first. The M1531 will not precede to execute a cycle until it detects ADSJ active.BRDYJO Group ABurst Ready. The assertion of BRDYJ means the current transaction is complete. The CPU terminates the cycle by receiving 1 or 4 active BRDYJs depending on different types of cycles.NAJO Group ANext Address. This signal is asserted by the M1531 to inform the CPU that pipelined cycles are ready for execution.AHOLDO Group ACPU AHold Request Output. It connects to the input of CPUs AHOLD pin and is actively driven for inquiry cycles.EADSJO Group AExternal Address Strobe. This signal is connected to the CPU EADSJ pin. During PCI cycles, the M1531 asserts this signal to proceed snooping.BOFFJO Group ACPU Back-Off. If BOFFJ is sampled active, CPU will float all its buses in the next clock. M1531 asserts this signal to request CPU floating all its output buses.HITMJI Group APrimary Cache Hit and Modified. When snooped, the CPU asserts HITMJ to indicate that a hit to a modified line in the data cache occurred. It is used to prohibit another bus master from accessing the data of this modified line in the memory until the line is completely written back.MIOJI Group AHost Memory or I/O. This bus definition pin indicates the current bus cycle is either memory or input/ output.DCJI Group AHost Data or Code. This bus definition pin is used to distinguish data access cycles from code access cycles.WRJI Group AHost Write or Read. When WRJ is driven high, it indicates the current cycle is a write. Inversely, if WRJ is driven low, a read cycle is performed.HLOCKJI Group AHost Lock. When HLOCKJ is asserted by the CPU, the M1531 will recognize the CPU is locking the current cycles.CACHEJI Group AHost Cacheable. This pin is used by the CPU to indicate the system that CPU wants to perform a line fill cycle or a burst write back cycle. If it is driven inactive in a read cycle, the CPU will not cache the returned data, regardless of the state of KENJ.