Acer Extensa 390 Service Guide

							Major Chips Description2-75 Table 2-865555 Pin Functions (continued)BallPin NameTypeActiveDescriptionP4,
U14,
U7,
J9-12
K9-12
L9-12
M9-12
Y1RGNDGNDInternal reference GND, should be tied to GNDH4,N4BVCCVCC-Power (Bus Interface), 3.3VU8DVCCVCC-Power (Flat Panel Interface), 3.3VD13
H17
N17MVCCVCC-Power (Memory Interface), 3.3V.U13VVCCVCC-Power (Video Interface), 3.3V.Video InterfaceV16VREFI/OHighVertical reference input for video data port.W17HREFInHighHorizontal reference input for video data portY18VCLKInHighClock input for video data port.V17PCLK(VCLKOUT)OutHighOutputs DCLK, or DCLK divided by 2.  See the
description for register XR60 for complete details.
Usable with either the video data port or the flat
panel interface.  May also be configured to output
VCLK in test mode.R18
U20
T19
R17
T18
U19
V20
T17
U18
V19
W20
W19
U17
V18
Y19
V18VP0
VP1
VP2
VP3
VP4
VP5
VP6
VP7
VP8
VP9
VP10
VP11
VP12
VP13
VP14
VP15In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
InHigh
High
High
High
High
High
High
High
High
High
High
High
High
High
High
HighData bus for video data port.
When used as a ZV-Port interface, VP0-7
correspond to Y0-7, and VP8-15 correspond to
UV0-7.Note:All signals listed above are powered by VVCC and GND.Boundary ScanA1TMSInHighTest  mode select for boundary scanB2TCLK(DCLKIN)InHighTest clock for boundary scan. Can be configured to
be used as an input for an externally provided
DCLK through a strapping option. See the
descriptions for registers XR70 and XRCF for
complete details 
						

							2-76Service GuideTable 2-865555 Pin Functions (continued)BallPin NameTypeActiveDescriptionB1TD1(MCLKIN)InHighTest data input for boundary scan. Can be
configured to be used as an input for an externally
provided MCLK through a strapping option and
register programming. See the descriptions for
registers XR70 and XRCF for complete detailsC2TDOInHighTest data out for boundary scan.D3TRST#InHighTest reset for boundary scan.Note:TMS, TCLK, TDI, TDO and TRST#, are powered by BVCC and GND.MiscellaneousE4STNDBT#InLowStandby Control Pin. Pull this pin low to place the
chip in  Standby Mode. A low to high transition on
the pin will cause change to exit standby mode,
host standby mode. and panel off mode.C3REFCLK(MCLKIN)InHighReference Clock Input. This pin serves as the input
for an external reference oscillator (usually
14.31818 MHz). All timings of the 65555 are
derived from this primary clock input source. Can
be configured to be used as an input for an
externally provided MCLK through a strapping
option and register programming. For normal
operation. TDI should be used as the input for an
externally provided MCLKV1GPIO0(ACTI)I/OHighGeneral Purpose l/O pin, or ACTI (Activity
Indicator).T4GPIO1(32KHz)I/OHighGeneral Purpose l/O pin, or 32KHz input: clock
input for refresh of non-self-refresh DRAMs and
panel power sequencingD6
C5
A12
K19N/C
N/C
N/C
N/Cn/a
n/a
n/a
n/an/a
n/a
n/a
n/aThese pins should be left open.Y20
D8
D17
A4
B5
D4
U16
C20
E17Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reservedn/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/an/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/aThese pins are reserved for future use, and should
not be connected.Note:STANDBY#, RCLK, GPIO0, and GPIO1 are powered by DVCC and GND. 
						

							Major Chips Description2-77 2.5 M38813
2.5.1 Overview
The M38813M4-XXXHP is an 8-bit single-chip microcomputer created in a silicon gate CMOS
process. Built into this single-chip microcomputer are:
· Serial l/O function (either clock synchronous or UART method selectable in software)
· 8-bit timers
· 8-bit Comparator
· Double Bus interface
The M38813M4-XXXHP is designed as a dedicated microcomputer for Keyboard controller. The
reduced power dissipation of the CMOS process also makes this microcomputer extremely useful
for applications utilizing battery power.
2.5.2 Description
The functions of the M38813M4-XXXHP are outlined in Table1.1.1. In this manual, the suffix HP
indicates a 0.5mm-lead pitch QFP.
Table 2-9M38813M4-XXXHP FunctionsParameterFunctionBasic instructions71Instruction execution time
0.5ms (shortest instruction, at 8MHz oscillation frequency)Oscillation frequency8MHz (max.)Memory sizeROM16384 bytes of user areaRAM512 bytesInput/output portsP0-P48-bit X 5P54-bit X 1P62-bit X 1Serial l/OClock synchronous or asynchronousTimers8-bit prescaler x 2 and 8-bit timer x 3Comparator4-bit resolution x 8 channelsBus interfaceTwo 8-bit Master CPU bus interfaceKey on wake up8 inputsInterrupts8 external, 9 internal, 1 softwareClock generation circuitBuilt-in (connect to external ceramic resonator or quartz crystal oscillator)Supply voltage
f(X
IN)=8MHz4.0 to 5.5Vf(X
IN)=4MHz2.7 to 5.5VPower dissipation40mW (at 8MHz oscillation frequency, typ.)Input/output characteristicsInput/output break-down voltage5V 
						

							2-78Service GuideTable 2-9M38813M4-XXXHP FunctionsParameterFunctionOutput current10mA (15mA for P2
4-P2
7)Operating temperature range
-20 to 85°CDevice structureCMOS silicon gatePackageM38813M4-XXXHP64-pin plastic molded QFP (0.5mm-
lead pitch)2.5.3 Pin Configuration
The Pin configuration of the M38813M4-XXXHP is shown in below.Figure 2-9M38813 Pin Diagram 
						

							Major Chips Description2-79 2.5.4 Pin Descriptions
The pin functions are listed in the table below.
Table 2-10M38813M4-XXXHP Pin DescriptionPinNameFunctionVcc, VssPower supplyPower supply inputs 2.7 to 5.5V to Vcc, and 0V to Vss.CNVssCNVssControls the operating mode of the chip. Normally connected to Vss or Vcc.RESETReset input
To enter the reset state, this pin must be kept L for more than 2ms (under
normal Vcc conditions). If the crystal or ceramic resonator requires more
time to stabilize, extend this L level time as appropriate..XIN
XOUTClock input
Clock outputInput and output signals to and from the internal clock generation circuit.
Connect a ceramic resonator or quartz crystal between the X
IN and X
OUT pins
to set the oscillation frequency. If an external clock is used, connect the
clock source to the X
IN pin and leave the X
OUT pin open.P0
0-P0
7I/O port P0An 8-bit CMOS l/O port. An l/O direction register allows each pin to be
individually programmed as either input or output. The input is CMOS/TTL
level, and output is CMOS 3 state / Nch open drainP1
0-P1
7I/O port P1An 8-bit CMOS l/O port with the same function as port P0. The input is
CMOS/TTL level, and output is CMOS 3 stateP2
O-P2
7I/O port P2An 8-bit CMOS l/O port with the same function as port P0. The input is
CMOS/TTL level, and output is CMOS 3 state. P
24-P
27 is the LED driver port
which capable of handling large current drive.P3c-P37I/O port P3An 8-bit CMOS l/O port with the same functions as port P0. The input is
CMOS level, and output is CMOS 3 state. This port is used as input of key
on wake up and comparator functions. Pull-up transistor can be controlled
by the program.P40-P47I/O port P4An 8-bit l/O port with the same functions as port P0. The input is CMOS TTL
level, and output of P4
0-P4
3,P4
6,P4
7 is Nch open drain. And The P4
4 and
P4
5 are also used as the control signal outputs to the master CPU by
selecting by the program.P5c-P53I/O port P5 ,An 4-bit CMOS l/O port with the same functions as port P0. The input is
CMOS level, and output is CMOS 3 state. The P5 also act as serial l/O
function pins by selecting by the program.P60-P61I/O port P6An 2-bit CMOS l/O port with the same functions as port P0. The input is
CMOS level, and output is CMOS 3 state. The P6
0 also act as the control
signal to the master CPU, and P6
1, act as l/O pin of the Timer X by
selecting by the program.Ao,So,E/R
W / R/WInput portThe control bus which control the interface between master CPU. The input
is CMOS/TTL level, and output is CMOS 3 state.DQo-DQ
7Input portAn 8-bit Input port used to interface with the master CPU. The input TTL
level, and output is CMOS/TTL level, and output is CMOS 3 state. 
						

							2-80Service Guide2.5.4.1 Functional Block DiagramFigure 2-10M38813 Block Diagram 
						

							Major Chips Description2-81 2.6 YMF715B-S
YMF715-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16 bit Sigma-delta
CODEC, MPU401 MIDI interface, joystick with timer, and a 3D enhanced controller including all the
analog components which is suitable for multi-media application. This LSI is fully compliant with
Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16 bit address decode, more
IRQs and DMAs in compliance with PC96. This LSI also supports the expandability, i.e. Zoomed
Video, Modem and CD-ROM interface in a Plug and Play manner, and power management (power
down, power save, partial power down, and suspend/resume) that is indispensable with power-
conscious application.
2.6.1 Features
· Built-in OPL3
· Supports Sound Blaster Game compatibility
· Supports Windows Sound System compatibility
· Supports Plug & Play ISA 1.0a compatibility
· Full Duplex operation
· Built-in MPU401 Compatible MIDI I/O port
· Built-in Joystick
· Built-in the 3D enhanced controller including all the analog components
· Supports multi-purpose pin function (Support 16-bit address decode, DAC interface for OPL4-
ML, Zoomed Video port, EEPROM interface, MODEM interface, IDE CD-ROM interface)
·  Hardware and software master volume control
· Supports monaural input
· 24 mA 1TL bus drive capability
· Supports Power Management(power down, power save, partial power down, and
suspend/resume)..
· +5V/ +3.3V power supply for digital, 5V power supply for analog.
· 100 pin SQFP package (YMF715-S) 
						

							2-82Service Guide2.6.2 Pin DiagramFigure 2-11YMF715 Block Diagram 
						

							Major Chips Description2-83 2.6.3 Pin Descriptions
Table 2-11YMF715 DescriptionsPin namePinsI/OTypeSizeFunctionISA bus interface: 36 pinsD7-08I/OTTL24mAData BusAl 1-012ITTL2mAAddress BusAEN1ITTL2mAAddress Bus Enable/IOW1
ISchmitt4mAWrite Enable/IOR1ISchmitt4mARead EnableRESET1ISchmitt4mAResetIRQ3,5,7,9,10,116TTTL12mAInterrupt requestDRQ0,1,33TTTL12mADMA Request/DACK0, 1,33ITTL2mADMA AcknowledgeAnalog Input & Output : 24 sinsOUTL1O--Left mixed analog outputOUTR1O--Right mixed analog outputVREFI1I--Voltage reference inputVREFO1O--Voltage reference outputAUXILlI--Left AUX1 inputAUX1RlI--Right AUX1 inputAIJX2LlI--Left AUX2 inputAUX2R1I--Right AUX2 inputLINEL1I--Left LINE inputLINER1I--Right LINE inputMIC1I--MIC inputMIN1I--Monaural inputTRECL1---Left Treble capacitorTRECR1---Right Treble-capacitorSBFLTL1---Left SBDAC filterSBFLTR1---Right SBDAC filterSYNSHL1---Left SYNDAC sample / hold capacitorSYNSHR1---Right SYNDAC sample / hold capacitorADFLTL1---Left input filterADFLTR1---Right input filterVOCOL1O--Left voice outputVOCORIO--Right voice outputVOCIL1I--Left voice inputVOCIR1I--Right voice inputMulti-purpose Dins: 13 pinsSEL2-03I+CMOS2mARefer to “Multi-purpose pins” section 
						

							2-84Service GuideTable 2-11YMF715 DescriptionsPin namePinsI/OTypeSizeFunctionMP9-0l0I+/OTTL4mARefer to “multi-purpose pins” sectionOthers: 27 pinsGPO - GP34IA--Game PortGP4- GP74I+Schmitt2mAGame PortRXD1I+Schmitt2rnAMIDI Data ReceiveTXD1OTTL4mAMIDI Data Transfer/VOLUP1I+Schmitt2mAHardware Volume (Up)/VOLDWlI+Schmitt2mAHardware Volume (Down)X3311ICMOS2mA33.8688 MHzX33O1OCMOS2mA33.8688 MHzX24I1ICMOS2mA24.576 MHzX24O1OCMOS2mA24.576 MHzAVDD2---Analog Power Supply (put on +5.0V)DVDD3---Digital Power Supply (put on +5.0 V or
+3.3V)AVSS2---Analog GNDDVSS4---Digital GNDNote:I+:Input Pin with Pull up Resistor
Schmitt: TTL-Schmitt input pin
T:TTL-tri-state output pin
O+:Output Pin with Pull up Resistor